參數(shù)資料
型號: A1280A-CQG172M
元件分類: FPGA
英文描述: FPGA, 1232 CLBS, 8000 GATES, 41 MHz, CQFP172
封裝: CERAMIC, CQFP-172
文件頁數(shù): 18/54頁
文件大?。?/td> 333K
代理商: A1280A-CQG172M
RadTolerant FPGAs
v3.1
1-21
Table 1-14 RT1280A, A1280A Output Module
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
11.0
13.0
ns
tDHL
Data-to-Pad LOW
13.9
16.4
ns
tENZH
Enable-to-Pad Z to HIGH
12.3
14.4
ns
tENZL
Enable-to-Pad Z to LOW
16.1
19.0
ns
tENHZ
Enable-to-Pad HIGH to Z
9.8
11.5
ns
tENLZ
Enable-to-Pad LOW to Z
11.5
13.6
ns
tGLH
G-to-Pad HIGH
12.4
14.6
ns
tGHL
G-to-Pad LOW
15.5
18.2
ns
dTLH
Delta LOW to HIGH
0.09
0.11
ns/pF
dTHL
Delta HIGH to LOW
0.17
0.20
ns/pF
CMOS Output Module Timing1
tDLH
Data-to-Pad HIGH
14.0
16.5
ns
tDHL
Data-to-Pad LOW
11.7
13.7
ns
tENZH
Enable-to-Pad Z to HIGH
12.3
14.4
ns
tENZL
Enable-to-Pad Z to LOW
16.1
19.0
ns
tENHZ
Enable-to-Pad HIGH to Z
9.8
11.5
ns
tENLZ
Enable-to-Pad LOW to Z
11.5
13.6
ns
tGLH
G-to-Pad HIGH
12.4
14.6
ns
tGHL
G-to-Pad LOW
15.5
18.2
ns
dTLH
Delta LOW to HIGH
0.17
0.20
ns/pF
dTHL
Delta HIGH to LOW
0.12
0.15
ns/pF
Notes:
1. Delays based on 50pF loading.
2. SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.
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