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參數(shù)資料
| 型號： | 9UMS9610CKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC48 |
| 封裝： | 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, MLF-48 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 134K |
| 代理商： | 9UMS9610CKLFT |
IDTTM/ICSTM PC MAIN CLOCK
1336—06/01/09
ICS9UMS9610
PC MAIN CLOCK
2
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
Logic Level
(V)
Input Level
Tolerance (V)
1
CPU_STOP#_3.3
IN
This active-low input stops all CPU clocks that are set to be stoppable.
3.3
2
CLKPWRGD#/PD_3.3
IN
This level sensitive strobe determines when latch inputs are valid and are
ready to be sampled. When high, this asynchronous input places the
device into the power down state.
3.3
3
X2
OUT Crystal output, Nominally 14.318MHz
N/A
4
X1
IN
Crystal input, Nominally 14.318MHz.
1.5
5
VDDREF_3.3
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
3.3
6
REF_3.3_2x
OUT 3.3V 14.318 MHz reference clock. Default 2 load drive strength
3.3
N/A
7
GNDREF
GND Ground pin for the REF outputs.
0
N/A
8
VDDCORE_1.5
PWR 1.5V power for the PLL core
1.5
9
FSC_L_1.5
IN
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. 1.5V Max input voltage.
1.5
10
TEST_MODE_1.5
IN
TEST_MODE is a real time input to select between Hi-Z and REF/N divider
mode while in test mode. Refer to Test Clarification Table. Max input
voltage is 1.5V.
1.5
3.3
11
TEST_SEL_1.5
IN
TEST_SEL: latched input to select TEST MODE. Max input voltage is 1.5V
1 = All outputs are tri-stated for test
0 = All outputs behave normally.
1.5
3.3
12
SCLK_3.3
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
3.3
13
SDATA_3.3
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
3.3
14
PWR 1.5V power for the PLL core
1.5
15
VDDIO_1.5
PWR Power supply for low power differential outputs, nominal 1.5V.
1.5
16
DOT96C_LPR
OUT
Complement clock of low power differential pair for 96.00MHz DOT clock.
No 50ohm resistor to GND needed. No Rs needed.
0.8
N/A
17
DOT96T_LPR
OUT
True clock of low power differential pair for 96.00MHz DOT clock. No
50ohm resistor to GND needed. No Rs needed.
0.8
N/A
18
GNDDOT
GND Ground pin for DOT clock output
0
N/A
19
GNDLCD
GND Ground pin for LCD clock output
0
N/A
20
LCD100C_LPR
OUT
Complement clock of low power differential pair for LCD100 SS clock. No
50ohm resistor to GND needed. No Rs needed.
0.8
N/A
21
LCD100T_LPR
OUT
True clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
0.8
N/A
22
VDDIO_1.5
PWR Power supply for low power differential outputs, nominal 1.5V.
1.5
23
VDDCORE_1.5
PWR 1.5V power for the PLL core
1.5
24
*CR#0_1.5
IN
1.5V Clock request for SRC0, 0 = enable, 1 = disable
1.5
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| 9UMS9610CKLF | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC48 |
| 9UMS9633BFILFT | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9UMS9633BKILFT | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC48 |
| 9UMS9633BFLFT | OTHER CLOCK GENERATOR, PDSO48 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 9UMS9633 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE |
| 9UMS9633BFILF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9UMS9633BFILFT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9UMS9633BFW3LFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE |
| 9UMS9633BKILF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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