參數資料
型號: 9S12B128DGV1
英文描述: 9S12B128 Device Guide
中文描述: 9S12B128設備指南
文件頁數: 53/128頁
文件大?。?/td> 1823K
代理商: 9S12B128DGV1
Device User Guide —9S12B128DGV1/D V01.11
53
2.2.8 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.2.9 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.2.10 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts
(lowpower)oscillatorisusedorwhetherPierceoscillator/externalclockcircuitryisused.Thestateofthis
pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an
external clock drive or a Pierce Oscillator. If input is a logic high a Colpitts oscillator circuit is configured
on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left
floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL.
Figure 2-4 Colpitts Oscillator Connections (PE7=1)
MCU
C
2
EXTAL
XTAL
Crystal or
ceramic resonator
VSSPLL
C
1
C
DC
*
* Due to the nature of a translated ground Colpitts oscillator a
DC voltage bias is applied to the crystal
Please contact the crystal manufacturer for crystal DC
bias conditions and recommended capacitor value C
DC
.
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