參數(shù)資料
型號(hào): 9Q512K32
廠商: Aeroflex Inc.
英文描述: UT9Q512K32 16Megabit SRAM MCM
中文描述: UT9Q512K32 16Megabit的SRAM億立方米
文件頁(yè)數(shù): 10/14頁(yè)
文件大?。?/td> 135K
代理商: 9Q512K32
10
t
EFDX
Assumptions & Notes:
1. G < V
IL
(max). If G > V
IH
(min) then Qn(7:0) will be in three-state for the entire cycle.
2. Either En scenario above can occur.
3. G high for t
AVAV
cycle.
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
A(18:0)
Wn
En
Dn(7:0)
APPLIED DATA
En
Qn(7:0)
t
WLQZ
t
ETEF
t
WLEF
t
DVEF
t
AVAV
3
t
AVET
t
AVET
t
ETEF
t
EFAX
t
EFAX
or
Notes:
1. 50pF including scope probe and test socket capacitance.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = V
DD
/2).
90%
Figure 6. AC Test Loads and Input Waveforms
Input Pulses
10%
< 5ns
< 5ns
V
LOAD
= 1.55V
300 ohms
50pF
CMOS
0.5V
V
DD
-0.05V
10%
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