參數(shù)資料
型號(hào)： 9LPRS525AFLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56
封裝： 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-56
文件頁(yè)數(shù)： 8/21頁(yè)
文件大?。?/td> 200K
代理商： 9LPRS525AFLFT
IDTTM
PC MAIN CLOCK
1484D—01/31/11
ICS9LPRS525
PC MAIN CLOCK
16
Byte 8 Device ID and Output Enable Register
Bit
Pin
Name
Description
Type
0
1
Default
7Device_ID3
R
0
6Device_ID2
R
0
5Device_ID1
R
0
4Device_ID0
R
0
3
Reserved
RW
-
0
2
Reserved
RW
-
0
1
SE1_OE
Output enable for SE1
RW
Disabled
Enabled
0
SE2_OE
Output enable for SE2
RW
Disabled
Enabled
0
Byte 9 Output Control Register
Bit
Pin
Name
Description
Type
0
1
Default
7PCIF5 STOP EN
Allows control of PCIF5 with assertion of
PCI_STOP#
RW
Free running
Stops with
PCI_STOP#
assertion
0
6
TME_Readback
Truested Mode Enable (TME) strap status
R
normal operation
no overclocking
Latch
5
REF Strength
Sets the REF output drive strength
RW
1X (2Loads)
2X (3 Loads)
1
4
Test Mode Select
Allows test select, ignores REF/FSC/TestSel
RW
Outputs HI-Z
Outputs = REF/N
0
3
Test Mode Entry
Allows entry into test mode, ignores
FSB/TestMode
RW
Normal operation
Test mode
0
2
IO_VOUT2
IO Output Voltage Select (Most Significant Bit)
RW
1
IO_VOUT1
IO Output Voltage Select
RW
0
IO_VOUT0
IO Output Voltage Select (Least Significant Bit)
RW
1
Byte 10 Stop Enable Register
Bit
Pin
Name
Description
Type
0
1
Default
7
SRC5_EN Readback
Readback of SRC5 enable latch
R
CPU/PCI Stop
Enabled
SRC5 Enabled
Latch
6
Reserved
RW
-
0
5
Reserved
RW
-
0
4
Reserved
RW
-
0
3
Reserved
RW
-
0
2
Reserved
RW
-
0
1
CPU 1 Stop Enable
Enables control of CPU1 with CPU_STOP#
RW
Free Running
Stoppable
1
0
CPU 0 Stop Enable
Enables control of CPU 0 with CPU_STOP#
RW
Free Running
Stoppable
1
Byte 11 iAMT Enable Register
Bit
Pin
Name
Description
Type
0
1
Default
7
PCI3_CFG1
R
Latch
6
PCI3_CFG0
R
Latch
5
Reserved
RW
--
0
4
Reserved
RW
-
1
3
CPU2_AMT_EN
Determines if CPU2 runs in M1 mode.
Only valid if ITP_EN=1. See Note.
RW
Does not Run
Runs
0
2
CPU1_AMT_EN
Determines if CPU1 runs in M1 mode. See Note.
RW
Does not Run
Runs
1
PCI-E_GEN2
Determines if PCI-E Gen2 compliant
R
non-Gen2
PCI-E Gen2
Compliant
1
0
CPU 2 Stop Enable
Enables control of CPU 0 with CPU_STOP#
RW
Free Running
Stoppable
1
NOTE: A value of '00' for Bit(3:2) in Byte 11 is reserved and not a valid configuration.
Reserved
Table of Device identifier codes, used for
differentiating between CK505 package options,
etc.
56-pin device
See Table 3: V_IO Selection
(Default is 0.8V)
See PCI3 Configuration Table 28
See PCI3 Configuration Table
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9LPRS525AGILF 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 56-PIN CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPRS525AGILFT 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 56-PIN CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPRS525AGLF 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 56-PIN CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPRS525AGLFT 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 56-PIN CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPRS535 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:48-pin CK505 for Intel Systems
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