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參數(shù)資料
| 型號(hào)： | 9LPRS502YKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC56 |
| 封裝： | ROHS COMPLIANT, MLF-56 |
| 文件頁數(shù)： | 27/29頁 |
| 文件大?。?/td> | 272K |
| 代理商： | 9LPRS502YKLFT |
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IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125A—02/19/08
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
7
Datasheet
MLF Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
X2
OUT
Crystal output, nominally 14.318MHz.
2
X1
IN
Crystal input, Nominally 14.318MHz.
3
VDDREF
PWR
Power pin for the REF outputs, 3.3V nominal.
4
REF0/FSLC/TEST_SEL
I/O
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable test mode.
Refer to Test Clarification Table.
5
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
6
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
7
PCI0/CR#_A
I/O
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or
SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in
byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve
as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs
address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
8
VDDPCI
PWR
Power supply pin for the PCI outputs, 3.3V nominal
9
PCI1/CR#_B
I/O
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or
SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in
byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve
as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs
address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
10
PCI2/TME
I/O
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
11
PCI3
OUT
3.3V PCI clock output.
12
PCI4/SRC5_EN
I/O
3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this
pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 29 and 30). The latched
value controls the pin function on pins 29 and 30 as follows
0 = PCI_STOP#/CPU_STOP#
1 = SRC5/SRC5#
13
PCI_F5/ITP_EN
I/O
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the
PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
14
GNDPCI
PWR
Ground for PCI clocks.
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