參數(shù)資料
型號： 9LPRS502YKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQCC56
封裝： ROHS COMPLIANT, MLF-56
文件頁數(shù)： 17/29頁
文件大?。?/td> 272K
代理商： 9LPRS502YKLFT
IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125A—02/19/08
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
24
Datasheet
Byte 20 CK505 PLL3 Spread Spectrum Control Register
Bit
Pin
Name
Description
Type
Default
7
Reserved
RW
0
6
SSP14
RW
X
5
SSP13
RW
X
4
SSP12
RW
X
3
SSP11
RW
X
2
SSP10
RW
X
1
SSP9
RW
X
0
SSP8
RW
X
Byte 21 M/N Enables
Bit
Pin
Name
Description
Type
Default
7
Reserved
RW
0
6
Reserved
RW
0
5
Reserved
RW
0
4
Reserved
RW
0
3
Reserved
RW
0
2
Reserved
RW
0
1
M/N Enable CPU
RW
0
M/N Enable
RW
0
Byte 22 CPU M/N Programming
Bit
Pin
Name
Description
Type
Default
7
N Div bit 8
PLL 1 M/N Programming
RW
X
6
N Div bit 9
(Intel PLL1 CPU)
RW
X
5M Div Bit 5
RW
X
4M Div Bit 4
RW
X
3M Div Bit 3
RW
X
2M Div Bit 2
RW
X
1M Div Bit 1
RW
X
0M Div Bit 0
RW
X
Byte 23 CPU M/N Programming
Bit
Pin
Name
Description
Type
Default
7
N Div bit 7
PLL 1 M/N Programming
RW
X
6
N Div bit 6
(Intel PLL1 CPU)
RW
X
5N Div bit 5
RW
X
4N Div bit 4
RW
X
3N Div bit 3
RW
X
2N Div bit 2
RW
X
1N Div bit 1
RW
X
0N Div Bit 0
RW
X
Bytes 24-62 Reserved
Byte 63 Special Power Management Features (Rev P Silicon and Higher)
Bit
Pin
Name
Description
RW
Default
7
Reserved
RW
0
6
Reserved
RW
0
5
Reserved
RW
0
4
Reserved
RW
0
3
Reserved
RW
0
2
Reserved
RW
0
1
SATA PLL
Power Management Feature
RW
Note
0
XTAL PD Control
Controls XTAL on/off in legacy PD
RW
1
*Accessing any SMBus bytes not shown in the datasheet could result in incorrect clock functions.
off
on
off
on
Note: Default is "off" for Rev P and "on" for Rev S.
01
-
1
-
0
-
Disable
Enable
01
Disable
Enable
01
-
01
--
These Spread Spectrum bits will program the spread
pecentage. Contact ICS for the correct values.
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