參數(shù)資料
型號: 9LPRS502YGLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件頁數(shù): 16/29頁
文件大?。?/td> 279K
代理商: 9LPRS502YGLFT
IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
23
Byte 15 CK505 PLL1 Spread Spectrum Control Register
Bit
Pin
Name
Description
Type
Default
7
SSP7
RW
X
6
SSP6
RW
X
5
SSP5
RW
X
4
SSP4
RW
X
3
SSP3
RW
X
2
SSP2
RW
X
1
SSP1
RW
X
0
SSP0
RW
X
Byte 16 CK505 PLL1 Spread Spectrum Control Register
Bit
Pin
Name
Description
Type
Default
7
Reserved
RW
0
6
SSP14
RW
x
5
SSP13
RW
X
4
SSP12
RW
X
3
SSP11
RW
X
2
SSP10
RW
X
1
SSP9
RW
X
0
SSP8
RW
X
Byte 17 CK505 PLL3 M/N Programming Register
Bit
Pin
Name
Description
Type
Default
7
N Div8
N Divider 8
RW
X
6
N Div9
N Divider 9
RW
X
5
M Div5
RW
X
4
M Div4
RW
X
3
M Div3
RW
X
2
M Div2
RW
X
1
M Div1
RW
X
0
M Div0
RW
X
Byte 18 CK505 PLL3 M/N Programming Register
Bit
Pin
Name
Description
Type
Default
7
N Div7
RW
X
6
N Div6
RW
X
5
N Div5
RW
X
4
N Div4
RW
X
3
N Div3
RW
X
2
N Div2
RW
X
1
N Div1
RW
X
0
N Div0
RW
X
Byte 19 CK505 PLL3 Spread Spectrum Control Register
Bit
Pin
Name
Description
Type
Default
7
SSP7
RW
X
6
SSP6
RW
X
5
SSP5
RW
X
4
SSP4
RW
X
3
SSP3
RW
X
2
SSP2
RW
X
1
SSP1
RW
X
0
SSP0
RW
X
1
-
01
-
01
-
0
-
01
-
01
-
The decimal representation of M and N Divider in Byte
17 and 18 will configure the VCO frequency. Default
at power up = latch-in or Byte 0 Rom table.
These Spread Spectrum bits will program the spread
pecentage. Contact ICS for the correct values.
These Spread Spectrum bits will program the spread
pecentage. Contact ICS for the correct values.
These Spread Spectrum bits will program the spread
pecentage. Contact ICS for the correct values.
The decimal representation of M and N Divider in Byte
17 and 18 will configure the VCO frequency. Default
at power up = latch-in or Byte 0 Rom table.
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