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參數(shù)資料
| 型號： | 9EX21801AKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, PQCC72 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLF-72 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 160K |
| 代理商： | 9EX21801AKLFT |
ICS9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
14
Datasheet
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-6578
pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks
or registered trademarks used to identify products or services of their respective owners.
Printed in USA
TM
Re v is io n His to ry
Rev.
Issu e Date Descrip tio n
Pag e #
0.1
4/29/2008
Initial R eleas e
-
0.2
5/1/2008
1. S M B us B y tes 11-16 are now res erv ed
2. S M B us Referenc es to 1:1 operating s et point regis ter are rem ov ed.
3. U pdated readbac k regis ters to m atc h new c ontrol pins
3. A dded Q P I phas e nois e s pec
4. S ignific ant c hanges to pinout to im prov e perform anc e
V arious
0.3
5/30/2008
1. U pdated/C orrec ted S M B us , filled in em pty by tes
2. U pdated F requenc y /F unc tionality T able
3. A dded S M B us A ddres s dec oding table and graph
4. C orrec ted P ow er hook up table.
V arious
0.4
6/3/2008
A dded rev is ion des ignator to orderng inform ation
12
0.5
12/8/2008
1. U pdated front page tex t
2. U pdated F unc tionality foot notes on P age 2.
3. D eleted duplic ate table on page 6.
4. C orrec ted D IF 0.7V C urrent M ode elec tric al c harac teris itc s - rem ov ed
sk ew s pec .
5. U pdated s k ew and Differential P aram eters T able to reflec t c har data,
added P LL B W and jitterpeak ing data to this table.
6. U pdated P has e J itter T able - rem ov ed F B D s pec s and added HiB W and
Low B W s ec tions
7. A dded S M B us A ddres s ing T able after page 9
1,2,6,7,8,
10
A
12/17/2008
1. U pdated P LL m ode input frequenc y range
2. N oted that M odulation frequenc y is the A llowable S pread M odulation
F requenc y . A dded foonote 3.
3. C orrec ted P CIe G en1 M ax phas e jitter s pec to be 86 ps ins tead of
108ps . 86ps is the derated lim it when us ing ~ 160K c y c les to c alc ulate the
v alue. R eleas ed to final - Rev A .
5,8
B
1/20/2010
1. C orrec ted P in Des c ription for P in 62. 0 = 133M , 1 = 100M .
4
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