參數(shù)資料
型號(hào)： 9531
廠商： NXP Semiconductors N.V.
英文描述： 8-bit I2C LED dimmer
中文描述： 8位I2C LED調(diào)光
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 154K
代理商： 9531
Philips Semiconductors
Product data
PCA9531
8-bit I
2
C LED dimmer
2003 Nov 10
6
POWER-ON RESET
When power is applied to V
DD
, an internal Power On Reset holds
the PCA9531 in a reset state until V
DD
has reached V
POR
. At this
point, the reset condition is released and the PCA9531 registers are
initialized to their default states, all the outputs in the off state.
EXTERNAL RESET
A reset can be accomplished by holding the RESET pin low for a
minimum of t
W
. The PCA9531 registers and I
2
C state machine will
be held in their default state until the RESET input is once again
high.
This input requires a pull-up resistor to V
DD
.
CHARACTERISTICS OF THE I
2
C-BUS
The I
2
C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 6).
SDA
SCL
SW00363
data line
stable;
data valid
change
of data
allowed
Figure 6. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 7).
System configuration
A device generating a message is a transmitter: a device receiving
is the receiver. The device that controls the message is the master
and the devices which are controlled by the master are the slaves
(see Figure 8).
SDA
SCL
SW00365
S
P
SDA
SCL
START condition
STOP condition
Figure 7. Definition of start and stop conditions
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
SW00366
I
2
C
MULTIPLEXER
SLAVE
Figure 8. System configuration
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