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參數(shù)資料
| 型號(hào)： | 9531 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit I2C LED dimmer |
| 中文描述： | 8位I2C LED調(diào)光 |
| 文件頁(yè)數(shù)： | 12/20頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | 9531 |
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Philips Semiconductors
Product data
PCA9531
8-bit I
2
C LED dimmer
2003 Nov 10
12
AC SPECIFICATIONS
SYMBOL
PARAMETER
STANDARD MODE I
2
C
BUS
MIN
0
FAST MODE
I
2
C BUS
MIN
0
UNITS
MAX
100
MAX
400
f
SCL
t
BUF
t
HD;STA
t
SU;STA
t
SU;STO
t
HD;DAT
t
VD;ACK
t
VD;DAT
(L)
t
VD;DAT
(H)
t
SU;DAT
t
LOW
t
HIGH
t
F
t
R
t
SP
Operating frequency
kHz
μ
s
μ
s
μ
s
μ
s
ns
Bus free time between STOP and START conditions
4.7
—
1.3
—
Hold time after (repeated) START condition
4.0
—
0.6
—
Repeated START condition setup time
4.7
—
0.6
—
Setup time for STOP condition
4.0
—
0.6
—
Data in hold time
Valid time for ACK condition
2
Data out valid time
3
Data out valid time
3
0
—
0
—
—
600
—
600
ns
—
600
—
600
ns
—
1500
—
600
ns
Data setup time
250
—
100
—
ns
μ
s
μ
s
ns
Clock LOW period
4.7
—
1.3
—
Clock HIGH period
4.0
—
0.6
—
Clock/Data fall time
—
300
20 + 0.1 C
b1
20 + 0.1 C
b1
—
300
Clock/Data rise time
—
1000
300
ns
Pulse width of spikes that must be suppressed by the
input filters
—
50
50
ns
Port Timing
t
PV
t
PS
t
PH
Output data valid
—
200
—
200
ns
Input data setup time
100
—
100
—
ns
μ
s
Input data hold time
1
—
1
—
Reset
t
W
t
REC
Reset pulse width
6
—
6
—
ns
Reset recovery time
0
—
0
—
ns
t
RESET4,5
Time to reset
400
—
400
—
ns
NOTES:
1. C
b
= total capacitance of one bus line in pF.
2. t
VD;ACK
= time for Acknowledgement signal from SCL low to SDA (out) low.
3. t
VD;DAT
= minimum time for SDA data out to be valid following SCL low.
4. Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
5. Upon reset, the full delay will be the sum of t
RESET
and the RC time constant of the SDA bus.
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