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參數(shù)資料
| 型號： | 952703BF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 217.9 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | GREEN, MO-118, SSOP-48 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 264K |
| 代理商： | 952703BF |
15
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
0813B—05/17/05
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next
high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2C configuration to be stoppable via assertion
of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state
of the stopped CPU signals is CPUT=Low and CPUC=High.There is to be no change to the output drive current values.The CPUT
will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 952703BFLF | 制造商:Integrated Device Technology Inc 功能描述:952703BFLF - Rail/Tube |
| 952703BFLFT | 制造商:Integrated Device Technology Inc 功能描述:952703BFLFT - Tape and Reel |
| 952704 | 制造商:Weidmuller 功能描述:TB11, UL 1604, 2GP,SS -EA - Bulk |
| 952705 | 制造商:Weidmuller 功能描述:TB12, UL 1604, 2GP,SS -EA - Bulk |
| 952706 | 制造商:Weidmuller 功能描述:TB13, UL 1604, 2GP,SS -EA - Bulk |
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