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參數(shù)資料
| 型號： | 952601YGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大小： | 227K |
| 代理商： | 952601YGLFT |
IDTTM
Progammable Timing Control HubTM for Next Gen P4TM Processor
701J—01/25/10
ICS952601
Programmable Timing Control HubTM for Next Gen P4TM Processor
12
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
PCI_Stop#
PCI_Stop# Control
0:all stoppable PCI
and SRC are
stopped
RW
Enable
Disable
1
Bit 6
PCICLK6
Output Control
RW
Disable
Enable
1
Bit 5
PCICLK5
Output Control
RW
Disable
Enable
1
Bit 4
PCICLK4
Output Control
RW
Disable
Enable
1
Bit 3
PCICLK3
Output Control
RW
Disable
Enable
1
Bit 2
PCICLK2
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK1
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK0
Output Control
RW
Disable
Enable
1
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
48MHz_USB
2x output drive
0=2x drive
RW
2x drive
normal
0
Bit 6
48MHz_USB
Output Control
RW
Disable
Enable
1
Bit 5
PCIF2
RW
FREE-RUN
STOPPABLE
0
Bit 4
PCIF1
RW
FREE-RUN
STOPPABLE
0
Bit 3
PCIF0
RW
FREE-RUN
STOPPABLE
0
Bit 2
PCICLK_F2
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK_F1
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK_F0
Output Control
RW
Disable
Enable
1
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
48MHZ_DOT
Output Control
RW
Disable
Enable
1
Bit 6
RESERVED
`
-
0
Bit 5
3V66_4/VCH
Select
Output Select
RW
3V66
VCH
0
Bit 4
3V66_4/VCH
Output Control
RW
Disable
Enable
1
Bit 3
3V66_3
Output Control
RW
Disable
Enable
1
Bit 2
3V66_2
Output Control
RW
Disable
Enable
1
Bit 1
3V66_1
Output Control
RW
Disable
Enable
1
Bit 0
3V66_0
Output Control
RW
Disable
Enable
1
Byte 4
31
9
8
PCI FREE-RUN
NING CONTROL
7
Byte 3
7,8,9,12,13,14,15,
18,19,20,37,38,
20
19
18
15
14
-
29
27
26
23
13
12
Byte 5
32
9
8
7
22
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