參數(shù)資料
型號： 935268625551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 61/82頁
文件大?。?/td> 1965K
代理商： 935268625551
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
64 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
DREQ is asserted once per N transfers (N is determined by the BURST value). Example shown here: N = 2.
Data strobe: DACK (read/write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 24. GDMA slave mode timing (BURST > 01H, MODE = 02H).
td1
tw1
tsu1
th1
tsu2
td2
th2
Tcy1
(write) DATA[15:0]
(read) DATA[15:0]
DREQ (2)
DACK(1)
DIOR/DIOW(1)
MGT505
HIGH
tw2
th3
(1) Programmable polarity: shown as active LOW.
Note: EOT should be valid for 36 ns (minimum) when DIOR/DIOW is active.
Fig 25. EOT timing in Split Bus mode.
(1) Programmable polarity: shown as active LOW.
Note: EOT should be valid for 36 ns (minimum) when RD/WR is active.
Fig 26. EOT timing in Generic Processor mode.
EOT(1)
DIOR/DIOW(1)
36 ns (min)
DREQ
th1
004aaa012
EOT(1)
RD/WR
004aaa013
36 ns (min)
DREQ
th1
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