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參數(shù)資料
| 型號(hào)： | 9240LP |
| 廠商： | Maxwell Technologies, Inc |
| 英文描述： | 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC |
| 中文描述： | 14位，10 MSPS的單片機(jī)的A / D轉(zhuǎn)換器與并口的ASIC |
| 文件頁(yè)數(shù)： | 2/18頁(yè) |
| 文件大?。?/td> | 495K |
| 代理商： | 9240LP |
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01.10.05 REV 6
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
9240LP
T
ABLE
1. 9240LP P
IN
D
ESCRIPTION
P
IN
N
UMBER
N
AME
D
ESCRIPTION
1
DVSS
AVSS
DVDD
AVDD
NC
DRVDD
CLK
LPTSTATUS
Digital Ground
Analog Ground
5V Digital Supply
5V Analog Supply
No Connect
Digital Output Driver Supply
Clock Input Pin
A 0 to 5V square-wave is output during the deci-
sion time and protect time. Normally low
The LPT circuit will crowbar the power supplies
to the 9240 for as long as a logic high is applied.
Used to verify operation of the LPT. Normally a
logical low or ground is applied to this input.
No Connect
Least Significant Data Bit (LSB)
Data Output Bits
Most Significant Data Bits (MSB)
Out of Range
No Connect
Reference Select
Reference I/O
Reference Common
No Connect
Power/Speed Programmng
Noise Reduction Pin
Noise Reduction Pin
Common-Mod Level (Mdsupply)
Protected Reference I/O
Analog Input Pin (+)
Analog Input Pin (-)
Protected 5V Digital Supply
Protected 5V Analog Supply
2, 29
3
4, 28
5
6
7
8
9
LPTBIT
10
11
NC
BIT 14
BIT 13-BIT 2
BIT 1
OTR
NC
SENSE
VREF
REFCOM
NC
BIAS
1
CAPB
CAPT
CML
LPTVREF
VINA
VINB
LPTDVDD
LPTAVDD
12-23
24
25
26, 27, 30
31
32
33
34, 38
35
36
37
39
40
41
42
43
44
1. See Speed/Power programmability section.
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