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參數(shù)資料
| 型號： | 89HPES16T4G2ZBBXG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA288 |
| 封裝： | 23 X 23 MM, 1 MM PITCH, GREEN, SBGA-288 |
| 文件頁數(shù)： | 26/31頁 |
| 文件大?。?/td> | 580K |
| 代理商： | 89HPES16T4G2ZBBXG |
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September 13, 2010
IDT 89HPES16T4G2 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES16T4G2. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Note: In the PES16T4G2, the three downstream ports are labeled port 2, port 4, and port 6.
Signal
Type
Name/Description
PE0RP[3:0]
PE0RN[3:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PE0TP[3:0]
PE0TN[3:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PE2RP[3:0]
PE2RN[3:0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE2TP[3:0]
PE2TN[3:0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PE4RP[3:0]
PE4RN[3:0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE4TP[3:0]
PE4TN[3:0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PE6RP[3:0]
PE6RN[3:0]
I
PCI Express Port 6 Serial Data Receive. Differential PCI Express receive
pairs for port 6.
PE6TP[3:0]
PE6TN[3:0]
O
PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 6.
PEREFCLKP[0]
PEREFCLKN[0]
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
This pin should be static and not change following the negation of
PERSTN.
Table 2 PCI Express Interface Pins
Signal
Type
Name/Description
MSMBADDR[4:1]
I
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
Table 3 SMBus Interface Pins (Part 1 of 2)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 89HPES16T4G2ZBBXG8 | 功能描述:開關(guān) IC - 各種 RoHS:否 制造商:Fairchild Semiconductor 開啟電阻（最大值）: 電源電壓-最大:4.4 V 電源電壓-最小:2.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:WLCSP-9 封裝:Reel |
| 89HPES16T4G2ZBBXGI | 制造商:Integrated Device Technology Inc 功能描述:484 BGA (GREEN) - Bulk |
| 89HPES16T4G2ZBBXI | 功能描述:開關(guān) IC - 各種 RoHS:否 制造商:Fairchild Semiconductor 開啟電阻（最大值）: 電源電壓-最大:4.4 V 電源電壓-最小:2.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:WLCSP-9 封裝:Reel |
| 89HPES16T4G2ZBBXI8 | 功能描述:開關(guān) IC - 各種 RoHS:否 制造商:Fairchild Semiconductor 開啟電阻（最大值）: 電源電壓-最大:4.4 V 電源電壓-最小:2.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:WLCSP-9 封裝:Reel |
| 89HPES16T4ZHBC | 功能描述:Switch Interfacing Interface 484-CABGA (23x23) 制造商:idt, integrated device technology inc 系列:PRECISE?? 包裝:托盤 零件狀態(tài):有效 應(yīng)用:開關(guān)接口 接口:PCI Express 電壓 - 電源:3.3V 封裝/外殼:484-BGA 供應(yīng)商器件封裝:484-CABGA（23x23） 安裝類型:表面貼裝 標(biāo)準(zhǔn)包裝:60 |
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