參數(shù)資料
型號(hào): 8535AG-21LFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 8535 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO14
封裝: 4.40 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-14
文件頁(yè)數(shù): 1/15頁(yè)
文件大?。?/td> 835K
代理商: 8535AG-21LFT
LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-
3.3V LVPECL CLOCK GENERATOR
ICS8535-21
IDT / ICS 3.3V LVPECL FANOUT BUFFER
1
ICS8535AG-21 REV. A FEBRUARY 24, 2009
General Description
The ICS8535-21 is a low skew, high performance
1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout
buffer and a member of the HiPerClockS family of
High Performance Clock Solutions from IDT. The
ICS8535-21 has two single-ended clock inputs. The
single-ended clock input accepts LVCMOS or LVTTL input levels
and translate them to 3.3V LVPECL levels. The clock enable is
internally synchronized to eliminate runt clock pulses on the output
during asynchronous assertion/deassertion of the clock enable
pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8535-21 ideal for those applications demanding well defined
performance and repeatability.
Features
Two differential 3.3V LVPECL outputs
Selectable CLK0 or CLK1 inputs for redundant and multiple
frequency fanout applications
CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 266MHz
Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels
Output skew: 20ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 1.6ns (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in both standard (RoHS 5) and lead-free (RoHS 6)
Block Diagram
HiPerClockS
ICS
Q0
Q1
CLK_EN
CLK_SEL
CLK1
CLK0
D
LE
Q
0
1
Pullup
Pulludown
1
2
3
4
5
6
7
VEE
CLK_EN
CLK_SEL
CLK0
VEE
CLK1
VCC
14
13
12
11
10
9
8
VCC
Q0
nc
Q1
VCC
Pin Assignment
ICS8535-21 14 Lead TSSOP
4.40mm x 5.0mm x 0.925mm package body
G Package
Top View
相關(guān)PDF資料
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