
R
Intel
82860 MCH Datasheet
9
Tables
Table 1. Maximum Memory Supported .............................................................................20
Table 2. Supported Direct RDRAM* Devices ....................................................................21
Table 3. MCH Processor System Bus-to-RAC Ratio.........................................................23
Table 4. MCH Processor-to-AGP/Hub Interface Ratio......................................................24
Table 5. Pin States during Reset.......................................................................................42
Table 6. MCH Configuration Space (Device 0) .................................................................51
Table 7. PAM Registers.....................................................................................................65
Table 8. Valid tRCD and tCAC combinations for 300 MHz and 400 MHz.........................79
Table 9. MCH Configuration Space (Device 1) .................................................................90
Table 10. MCH Configuration Space (Device 2) .............................................................106
Table 11. MCH Configuration Space (Device 3) .............................................................122
Table 12. SMM Space Address Ranges .........................................................................147
Table 13. Direct RDRAM* Device Grouping....................................................................155
Table 14. Sideband CMOS Signal Description................................................................156
Table 15. CMD Signal Value Decode..............................................................................157
Table 16. ROWA Packet for Activating (sensing) a Row (i.e., AV = 1) ...........................159
Table 17. ROWR Packet for Other Operations (i.e., AV = 0)..........................................159
Table 18. Row Packet Encodings....................................................................................160
Table 19. COLC Packet...................................................................................................161
Table 20. COLC Packet Field Encodings........................................................................161
Table 21. COLM Packet and COLX Packet Field Encodings..........................................162
Table 22. Data Packet.....................................................................................................162
Table 23. DRAM Operating States..................................................................................163
Table 24. Direct RDRAM* Device Power Management States.......................................164
Table 25. Absolute Maximum Ratings.............................................................................167
Table 26. Intel
860 Chipset Package Thermal Resistance............................................168
Table 27. DC Characteristics Functional Operating Range (VCC1_8 = 1.8V ±5%;
Tdie = 110 °C)..........................................................................................................168
Table 28. Signal Groups..................................................................................................169
Table 29. DC Characteristics at VCC1_8 = 1.8V ±5% ....................................................171
Table 30. MCH Alphabetical Ballout List .........................................................................181
Table 31. Example Nominalization Table........................................................................192
Table 32. MCH
L
Pkg
Data for Rambus* Channel A and Rambus Channel B ................194
Table 33. MCH System Bus Signal Normalized Trace Length Data per Group..............195
Table 34. MCH System Bus Signal Normalized Trace Length Data per Group..............196
Table 35. MCH 16-bit Hub Interface_B Signal Normalized Trace Length Data ..............197
Table 36. MCH 16-Bit Hub Interface_C Signal Normalized Trace Length Data..............198
Table 37. XOR Chain 1 ...................................................................................................200
Table 38. XOR Chain 2 ...................................................................................................202
Table 39. XOR Chain 3 ...................................................................................................204
Table 40. XOR Chain 4 ...................................................................................................205
Table 41. XOR Chain 5 ...................................................................................................207
Table 42. XOR Chain 6 ...................................................................................................208
Table 43. XOR Chain 7 ...................................................................................................210
Table 44. XOR Chain 8 ...................................................................................................211