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參數(shù)資料
| 型號： | 7P512CFA4500C25 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 256M X 16 FLASH 3V PROM CARD, 250 ns, XMA50 |
| 封裝： | CARD-50 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 264K |
| 代理商： | 7P512CFA4500C25 |
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White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
INTERFACE SIGNAL TIMING
There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, a direct mapped
I/O transfer and a memory access. The two timing sequences are explained in detail in the PCMCIA PC Card
Standard. The PC Card conforms to the timing in that reference document.
PC CARD INTERFACE
Parameter
Symbol
IEEE Symbol
300ns
Min. ns
Max. ns
Read Cycle Time
tC(R)
TAVAV
300
Address Access Time
tA(A)
TAVQV
300
Card Enable Access Time
tA(CE)
TELQV
300
Output Enable Access Time
tA(OE)
TGLQV
150
Output Disable Time from CE
tDIS(CE)
TEHQZ
100
Output Disable Time from OE
tDIS(OE)
TGHQZ
100
Address Setup Time
tSU(A)
tAVWL
30
Output Enable Time from CE
tEN(CE)
tELQNZ
5
Output Enable Time from OE
tEN(OE)
tGLQNZ
5
Data Valid from Address Change
tV(A)
tAXQX
0
ATTRIBUTE MEMORY READ TIMING
NOTE: All times are in nanosecond. Dout signifies data provided by the PC Card to the system. The CE signal or both
the OE signal & the WE signal must be de-asserted between consecutive cycle operations.
An
REG
CE
OE
DOUT
tC (R)
tA (A)
tSU (A)
tA (CE)
tV (A)
tEN (CE)
tEN (OE)
tA (OE)
tDIS (CE)
tDIS (OE)
ATTRIBUTE MEMORY READ TIMING DIAGRAM
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