參數(shù)資料
型號(hào)： 7P512CFA4500C25
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： PROM
英文描述： 256M X 16 FLASH 3V PROM CARD, 250 ns, XMA50
封裝： CARD-50
文件頁(yè)數(shù)： 27/32頁(yè)
文件大?。?/td> 264K
代理商： 7P512CFA4500C25
4
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
Symbol
Type
Name and Function
A0 - A10
INPUT
ADDRESS BUS: These address lines along with the REG signal are used to select the following: The I/O port
address registers within the PC Storage Card, the memory mapped port address registers within the PC
Storage Card, a byte in the Cards information structure and its configuration control and status registers. This
signal is the same as the PC Card Memory Mode signal in PC Card I/O mode. In True IDE Mode only A [2:0]
are used to select the one of eight registers in the Task File, the remaining address lines should be grounded
by the host.
D0 - D15
INPUT/
DATA BUS: These signal lines carry the Data, Commands and Status information between the host and the
OUTPUT
controller. D0 is the LSB of the even byte of the word. D8 is the LSB of the odd byte of the word.
This signal is the same as the PC Card memory mode signal in PC Card I/O mode. In True IDE mode, all Task
File operations occur in byte mode on the low order bus D0-D7 while all data transfers are 16 bit using D0D15.
CE1, CE2
INPUT
CARD ENABLE: CE1 and CE2 are card select signals, active low. These input signals are used both to select
the card and to indicate to the card whether a byte or a word operation is being performed. CE2 always
accesses the odd byte of the word. CE1 accesses the even byte or the Odd byte of the word depending on
A0 and CE2. A multiplexing scheme based on A0, CE1, CE2 allows 8 bit hosts to access all data on
D0-D7. This signal is the same as the PC card memory mode signal in PC Card I/O mode. In the True IDE
mode, CE1 is the chip select for the task file registers while CE2 is used to select the Alternate Status
Register and the Device Control Register.
OE, ASTEL
INPUT
OUTPUT ENABLE, ATA SELECT: OE is used for the control of data read in Attribute area or Common memory
area. To enable True IDE Mode this input should be grounded by the host (in power up).
WE
INPUT
WRITE ENABLE: WE is used for the control of data write in Attribute memory area or Common memory area.
This is a signal driven by the host and used for strobing memory write data to the registers of the PC Card
when the card is configured in the memory interface mode. It is also used for writing the configuration
registers. In PC Card I/O mode, this signal is used for writing the configuration registers. In True IDE mode,
this input signal is not used and should be connected to VCC by the host.
IORD
INPUT
I/O READ: IORD is used for control of read data in the Task File area. This card does not respond to IORD
until I/O card interface setting up.
IOWRINPUT
I/O WRITE: IOWR is used for control of data write in the Task File area. This card does not respond to IOWR
until I/O card interface setting up. This signal is not used in memory mode. The I/O write strobe pulse is used
to clock I/O data on the card data bus into the CF Card controller registers when the CF Card is configured to
use the I/O interface. The clocking will occur on the negative to positive edge of the signal (trailing edge). In
True IDE mode, this signal has the same function as in PC Card I/O Mode.
RDY/BSY,
OUTPUT
READY/BUSY, INTERRUPT REQUEST: In memory mode, this signal is set high when the CF Card is
IREQ, INTRQ
ready to accept a new data transfer operation and held low when the card is busy. The host memory card
socket must provide a pull-up resistor. At power up and at reset, the RDY/BSY signal is held low (busy) until
the CF Card has completed its power up or reset function. No access of any type should be made to the CF
Card during this time. The RDY/BSY signal is held high (disabled from being busy) whenever the following
condition is true: The CF Card has been powered up with RESET continuously disconnected or asserted. I/O
operation - After the CF Card has been configured for I/O operation, this signal is used as Interrupt request.
This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. In True IDE
mode, this signal is the active high Interrupt request to the host.
CD1, CD2
OUTPUT
CARD DETECTION: CD1 and CD2 are the card detection signals. CD1 and CD2 are connected to ground in
this card, so the host can detect if the card is inserted or not.
WP, IOIS16
OUTPUT
WRITE PROTECT, 16 BIT I/O PORT: In memory card mode, WP is held low because this card does not have a
write protect switch. In the I/O card mode, IOIS16 is asserted when Task File registers are accessed in 16-bit
mode. In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer
cycle.
REG
INPUT
ATTRIBUTE MEMORY AREA SELECTION: REG should be high level during common memory area accessing,
and low level during Attribute area accessing. The attribute memory area is located only in an even address, so
D0 to D7 are valid and D8 to D15 are invalid in the word access mode. Odd addresses are invalid in the byte
access mode. The signal must also be active (low) during I/O cycles when the I/O address is on the Bus. In
True IDE Mode this input signal is not used and should be connected to VCC.
BVD2, SPKR,
INPUT/
BATTERY VOLTAGE DETECTION, DIGITAL AUDIO OUTPUT, DISK ACTIVE/SLAVE PRESENT: In memory card
DASP
OUTPUT
mode, BVD2 outputs the battery voltage status in the card. This card has no battery, so this output is high
level constantly. In the I/O card mode, SPKR is held High because this card does not have digital audio output.
In True IDE Mode DASP is the Disk Active/Slave Present signal in the Master/Slave handshake protocol.
RESET,
INPUT
RESET: By assertion of the RESET signal, all registers of this card are cleared and the RDY/BSY signal turns
RESET
to high level. In True IDE Mode RESET is the active low hardware reset from the host.
INTERFACE SIGNALS DESCRIPTION
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