參數(shù)資料
型號： 78Q2133/F
廠商： Maxim Integrated Products
文件頁數(shù)： 14/38頁
文件大?。?/td> 0K
描述： TXRX 10/100 MDIX 3.3V IND 32-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 490
類型： PHY 收發(fā)器
驅(qū)動器/接收器數(shù)： 4/4
規(guī)程： IEEE 802
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 管件
DS_21x3_001
78Q2123/78Q2133 Data Sheet
Rev. 1.6
21
3.10 MR18: Diagnostic Register
Bit
Symbol
Type
Default
Description
18.15:13
RSVD
R
0
Reserved
18.12
ANEGF
RC
0
Auto-Negotiation Fail Indication: This bit is set when
auto-negotiation completes and no common technology was
found. It remains set until read.
18.11
DPLX
R
0
Duplex Indication: This bit indicates the result of the
auto-negotiation for duplex arbitration as follows:
0 = Half-duplex was the highest common denominator
1 = Full-duplex was the highest common denominator
18.10
RATE
R
0
Rate Indication: This bit indicates the result of the auto-
negotiation for data rate arbitration as follows:
0 = 10Base-T was the highest common denominator
1 = 100Base-TX was the highest common denominator
18.9
RXSD
R
0
Receiver Signal Detect Indication: In 10Base-T mode, this
bit indicates that Manchester data has been detected. In
100Base-TX mode, it indicates that the receive signal
activity has been detected (but not necessarily locked on
to).
18.8
RX_LOCK
R
0
Receive PLL Lock Indication: Indicates that the Receive
PLL has locked onto the receive signal for the selected
speed of operation (10Base-T or 100Base-TX).
18.7:0
RSVD
R
00h
Reserved: Must set to ‘00h’.
3.11 MR19: Transceiver Control
Bit
Symbol
Type
Default
Description
19.15:14
TXO[1:0]
R/W
01
Transmit Amplitude Selection: Sets the transmit output
amplitude to account for transmit transformer insertion loss.
00 = Gain set for 0.0dB of insertion loss.
01 = Gain set for 0.4dB of insertion loss.
10 = Gain set for 0.8dB of insertion loss.
11 = Gain set for 1.2dB of insertion loss.
19.13:0
RSVD
R
XXXh
Reserved
3.12 MR20: Reserved
Bit
Symbol
Type
Default
Description
20.15:0
Reserved
NA
XXXXh
Reserved: must be 0000h.
3.13 MR21: Reserved
Bit
Symbol
Type
Default
Description
21.15:0
Reserved
NA
XXXXh
Reserved: must be 0000h.
3.14 MR22: Reserved
Bit
Symbol
Type
Default
Description
22.15:0
Reserved
NA
XXXXh
Reserved: must be 0000h.
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