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參數(shù)資料
| 型號： | 78P2351-DB/ECLM |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DEMO 78P2351 W/OPT MODULE |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
Page: 14 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
REGISTER DESCRIPTION (continued)
ADDRESS 1-1: SIGNAL CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7
TCMIINV
R/W
0
Transmit CMI Inversion:
This bit will flip the polarity of the transmit CMI data outputs at CMIP/N.
For debug use only.
0: Normal
1: Invert
6
RCMIINV
R/W
0
Receive CMI Inversion:
This bit will flip the polarity of the receive CMI data inputs at RXP/N. For
debug use only.
0: Normal
1: Invert
5
LOLOR
R/W
0
Receive Loss of Lock/Signal Override:
When high, the RXLOL and RXLOS signals will always remain low.
0: Normal
1: Forces LOS and LOL outputs to be low and resets counters
NOTE: For reliable operation of the Rx LOL detection circuitry, one must
manually reset the LOL counter by toggling this bit upon power-up or
initialization.
4
RLBK
R/W
0
3
LLBK
R/W
0
Analog Loopback Selection:
RLBK LLBK
0
Normal operation
1
0
Remote Loopback Enable: Recovered receive data
is looped back to the transmit driver
0
1
Local Loopback Enable: The transmit data is
looped back and used as the input to the receiver.
2
RCLKP
R/W
0
Receive Clock Inversion Select:
This bit will invert the receive output clock.
0: Normal. Data clocked out on falling edge of receive clock.
1: Invert. Data clocked out on the rising edge of receive clock.
1
TCLKP
R/W
0
Transmit Clock Inversion Select:
This bit will invert the transmit input system clock.
0: Normal. Data is clocked in on rising edge of the transmit clock.
1: Invert. Data is clocked in on the falling edge of the transmit clock.
0
FRST
R/W
0
FIFO Reset:
0: Normal operation
1: Reset FIFO pointers to default locations.
This reset should be initiated anytime the transmitter or IC powers up to
ensure the FIFO is centered after internal VCO clocks and external
transmit clocks are stable.
NOTES: Transmit monitor port will also be affected by FRST, FIFO
resets not required for Plesiochronous Serial Mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 78P2351-IGT | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Single Channel OC-3/ STM1-E/ E4 LIU |
| 78P2351-IGT/F | 功能描述:接口 - 專用 Single Ch OC-3/STM-1e/E4 LIU RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| 78P2351-IGTR | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Single Channel OC-3/ STM1-E/ E4 LIU |
| 78P2351-IGTR/F | 功能描述:接口 - 專用 Single Ch OC-3/STM-1e/E4 LIU RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| 78P2351R | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Serial 155M NRZ to CMI Converter |
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