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Rev.2.00
REJ03B0202-0200
Mar 05, 2007
Page 48 of 70
7549 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig 63.
φ
SOURCE state transition
X
IN
HSOCO “S”
LSOCO “S”
xx10x011
X
IN
“O”
HSOCO “O”
LSOCO
xx00x000
X
IN
“S”
HSOCO “S”
LSOCO
xx00x110
X
IN
“S”
HSOCO
LSOCO “S”
xx01x101
X
IN
HSOCO “O”
LSOCO “S”
xx10x001
X
IN
“O”
HSOCO “S”
LSOCO
xx00x010
X
IN
“S”
HSOCO “O”
LSOCO
xx00x100
X
IN
HSOCO “O”
LSOCO “O”
xx10x000
X
IN
“O”
HSOCO
LSOCO “O”
xx01x000
X
IN
HSOCO “S”
LSOCO “O”
xx10x010
X
IN
“S”
HSOCO
LSOCO “O”
xx01x100
X
IN
“O”
HSOCO
LSOCO “S”
xx01x001
High-speed on-chip oscillator (HSOCO): oscillation start
b1=0
X
IN
oscillation:
oscillation start (Note 3)
b2=0
Low-speed on-chip oscillator
(LSOCO): oscillation start
b0=0
φ
Sslco
HO (5401
X
IN
(5410
(Nt )
X
I
S
O
(
HSOCO
Osclaton
(b1=0)
Stop
(b1=1)
sSOURC
(5HOCO
(LOCO
L
S
O
(
HSOCO
Osclaton
(b1=0)
(bStop
φ
SOURCE selection
X
IN
(b5,4=1,0)
(Note 3)
LSOCO
(b5,4=0,0)
LSOCO
S(b0=1)
Osclaton
(b0=0)
X
IN
Osclaton
(b2=0)
(bStop
b2
b
b5,4
(Note 3)
b,
b,
(oe3
b1,0
b
(Nb0
(Nt )
(Nb0
b
b
b2
b0
(Note 1)
b,
(Nt )
b2,0 (Note 1)
b2
b,
b2,1
(Notb0
b2,0 (Note 1)
b,
b,
[Remarks]
Reset released
b2
State transition of clock mode register CLKM (address: 0037
16
) setting value and clock
(When X
IN
oscillation is used. The same applies when X
CIN
oscillation and external clock input are used.)
X
IN
“O”
HSOCO “S”
LSOCO
xx00x010
b5,4
(Note 3)
(Note 2)
X
IN
, HSOCO, LSOCO, and respective oscillation and stop status in each mode are shown.
The symbol (
) indicates
φ
SOURCE (oscillation) selected by the clock selection bits.
“O” indicates oscillation and “S” indicates stopping.
The values such as “xx00x010” indicate the values (binary) of the clock mode register in the mode.
The arrow (bx) indicates a bit in the clock mode register, showing a transition by changing the bit values.
Entering the mode should be performed according to the arrows. Wait mode and stop mode can be
entered from all modes, and the original mode is returned after exiting.
Notes 1: When stopping the low-speed on-chip oscillator is disabled by the low-speed on-chip oscillator control bit (bit 4 in FSROM2),
“1” cannot be written to the bit 0 in CLKM. The low-speed on-chip oscillator does not stop even in stop mode.
2: After releasing reset, the low-speed on-chip oscillator is selected as
φ
SOURCE and divided by 8 is selected as the CPU clock.
3: When the oscillation pins not used is set by the oscillation method selection bits (bits 1 and 0 in FSROM1), “10” cannot be
written to bits 5 and 5 in CLKM. To use X
IN
oscillation as
φ
SOURCE, switch after X
IN
oscillation is stabilized. Supply a stable
clock when an external clock is used.
4: Do not change the values of the clock selection bits (bits 5 and 4) in CLKM and the individual clock oscillation control bits
(bits 2 to 0) at the same time using a singe instruction. Always use different instructions to rewrite these values.
5: Wait until the oscillation used in the destination mode is stabilized before entering.
Wait mode
Low-speed on-chip oscillator: Status before executing WIT instruction is kept
High-speed on-chip oscillator: Status before executing WIT instruction is kept
X
IN
oscillation: Status before executing the WIT instruction is kept
Stop mode
Low-speed on-chip oscillator: Stopped (Note 1)
High-speed on-chip oscillator: Stopped
X
IN
oscillation: Stopped
b5,4
(Note 3)