
7540 Group User
’
s Manual
3-104
APPENDIX
3.5 List of registers
Fig. 3.5.12 Structure of Timer A mode register
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
Name
Timer A mode register (TAM) [Address : 1D
16
]
Timer A mode register
4
6
7
0
0
0
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously
measurement mode
b5 b4
5
0
Timer A operating mode bits
CNTR
1
active edge switch bit
The function depends on the
operating mode.
(Refer to Table 3.5.1)
Timer A count stop bit
0 : Count start
1 : Count stop
1
2
3
0
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are
“
0
”
.
0
0
Timer A operating modes
Timer mode
Period measurement mode
Event counter mode
Pulse width HL continuously
measurement mode
CNTR
1
active edge switch bit
“
0
”
CNTR
1
interrupt request occurrence: Falling edge
; No influence to timer A count
“
1
”
CNTR
1
interrupt request occurrence: Rising edge
; No influence to timer A count
“
0
”
Pulse output start: Falling edge period measurement
CNTR
1
interrupt request occurrence: Falling edge
“
1
”
Pulse output start: Rising edge period measurement
CNTR
1
interrupt request occurrence: Rising edge
“
0
”
Timer A: Rising edge count
CNTR
1
interrupt request occurrence: Falling edge
“
1
”
Timer A: Falling edge count
CNTR
1
interrupt request occurrence: Rising edge
“
0
”
CNTR
1
interrupt request occurrence: Falling edge and rising edge
; No influence to timer A count
“
1
”
CNTR
1
interrupt request occurrence: Rising edge and falling edge
; No influence to timer A count
Table 3.5.1 CNTR
1
active edge switch bit function