
7540 Group User
’
s Manual
2-42
APPLICATION
2.4 Timer X
Fig. 2.4.4 Structure of Timer X mode register
Timer X operating modes
Timer mode
Pulse output mode
Event counter mode
Pulse width measurement mode
CNTR
0
active edge switch bit (bit 2 of address 2B
16
) contents
“
0
”
CNTR
0
interrupt request occurrence: Falling edge
; No influence to timer count
“
1
”
CNTR
0
interrupt request occurrence: Rising edge
; No influence to timer count
“
0
”
Pulse output start: Beginning at
“
H
”
level
CNTR
0
interrupt request occurrence: Falling edge
“
1
”
Pulse output start: Beginning at
“
L
”
level
CNTR
0
interrupt request occurrence: Rising edge
“
0
”
Timer X: Rising edge count
CNTR
0
interrupt request occurrence: Falling edge
“
1
”
Timer X: Falling edge count
CNTR
0
interrupt request occurrence: Rising edge
“
0
”
Timer X:
“
H
”
level width measurement
CNTR
0
interrupt request occurrence: Falling edge
“
1
”
Timer X:
“
L
”
level width measurement
CNTR
0
interrupt request occurrence: Rising edge
Table 2.4.1 CNTR
0
active edge switch bit function
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
2
3
4
5
6
7
Name
0
0
0
0
Timer X mode register (TXM) [Address : 2B
16
]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are
“
0
”
.
Timer X mode register
0
0
0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement
mode
b1 b0
1
0
Timer X operating mode bits
CNTR
0
active edge switch bit
The function depends on the
operating mode.
(Refer to Table 2.4.1)
Timer X count stop bit
0 : Count start
1 : Count stop
0 : Output invalid (I/O port)
1 : Output valid (Inverted CNTR
0
output)
P0
3
/TX
OUT
output valid bit