參數(shù)資料
型號(hào)： 7531GROUP
英文描述： 250MA CMOS LDO, ISUPPLY 1UA & 2% VOUT ACCURACY, -40C to +125C, 3-SOT-89, T/R
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 24/64頁(yè)
文件大?。?/td> 633K
代理商： 7531GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7531 Group
MITSUBISHI MICROCOMPUTERS
24
G
Serial I/O2
The serial I/O2 function can be used only for clock synchronous se-
rial I/O.
For clock synchronous serial I/O2 the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8 bits which control various
serial I/O functions.
Set “0” to bit 3 to receive.
At reception, clear bit 7 to “0” by writing a dummy data to the serial I/
O2 register after completion of shift.
Bit 7 is set to “1” a half cycle (of the shift clock) earlier than comple-
tion of shift operation. Accordingly, when using this bit to confirm
shift completion, a half cycle or more of the shift clock must pass
after confirming that this bit is set to “1”, before performing read/
write to the serial I/O2 register.
Fig. 27 Structure of serial I/O2 control registers
Fig. 28 Block diagram of serial I/O2
Internal synchronous clock selection bits
000 : f(X
IN
)/8
001 : f(X
IN
)/16
010 : f(X
IN
)/32
011 : f(X
IN
)/64
110 : f(X
IN
)/128
111 : f(X
IN
)/256
S
DATA
pin selection bit (Note)
0 : I/O port / S
DATA
input
1 : S
DATA
output
b7 b0
Not used
(returns “0” when read)
Transfer direction selection bit
0 : LSB first
1 : MSB first
S
CLK
pin selection bit
0 : External clock (S
CLK
is an input)
1 : Internal clock (S
CLK
is an output)
Transmit / receive shift completion flag
0 : shift in progress
1 : shift completed
Note :
When using it as a S
DATA
input, set the port P1
3
direction register to “0”.
Serial I/O2 control register
(SIO2CON: address 0030
16
, initial value: 00
16
)
“1”
“0”
“0”
“1”
“0”
“1”
1/8
1/16
1/32
1/64
1/128
1/256
X
IN
Data bus
Serial I/O2
interrupt request
S
DATA
pin selection bit
Serial I/O counter 2 (3)
Serial I/O shift register 2 (8)
S
CLK
pin selection bit
Internal synchronous
clock selection bits
D
P1
2
/S
CLK
P1
3
/S
DATA
P1
2
latch
S
CLK pin
selection bit
S
CLK
P1
3
latch
S
DATA
pin selection bit
相關(guān)PDF資料
PDF描述
7531 250mA CMOS LDO, Isupply 1uA and 2% Vout Accuracy, -40C to +125C, 3-SOT-23, T/R
7532 Low Quiescent Current LDO, -40C to +125C, 3-SOT-23, T/R
7533 250mA CMOS LDO, lsupply 1uA and 2% Vout Accuracy, -40C to +125C, 3-SOT-23, T/R
753252 250mA CMOS LDO, lsupply 1uA and 2% Vout Accuracy, -40C to +125C, 3-SOT-23, T/R
7535 Low Quiescent Current LDO, -40C to +125C, 3-SOT-23, T/R
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