參數(shù)資料
型號(hào)： 7513
英文描述： 7513 Group Datasheet Datasheet 1067K/FEB.06.01
中文描述： 7513組數(shù)據(jù)表數(shù)據(jù)表1067K/FEB.06.01
文件頁(yè)數(shù)： 26/66頁(yè)
文件大?。?/td> 1067K
代理商： 7513
25
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7513 Group
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
(1) Timer Mode
The timer counts f(X
IN
)/16 (or f(X
CIN
)/16 in low-speed mode).
(2) Pulse Output Mode
Each time the timer underflows, a signal output from the CNTR
0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the port shared with the CNTR
0
pin to input.
(3) Event Counter Mode
The timer counts signals input through the CNTR
0
pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the port
shared with the CNTR
0
pin to input.
(4) Pulse Width Measurement Mode
The count source is f(X
IN
)/16 (or f(X
CIN
)/16 in low-speed mode). If
CNTR
0
active edge switch bit is “0”, the timer counts while the in-
put signal of CNTR
0
pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR
0
pin is at “L”. When using a timer in this
mode, set the port shared with tha CNTR
0
pin to input.
G
Timer X write control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, unexpected value may be set in
the high-order counter when the writing in high-order latch and the
underflow of timer X are performed at the same timing.
I
Notes on CNTR
0
interrupt active edge selection
CNTR
0
interrupt active edge depends on the CNTR
0
active edge
switch bit.
G
Real time port control
While the real time port function is valid, data for the real time port
are output from ports P5
2
and P5
3
each time the timer X
underflows. (However, if the real time port control bit is changed
from “0” to “1”, data are output without the timer X.) When the data
for the real time port is changed while the real time port function is
valid, the changed data are output at the next underflow of timer
X.
Before using this function, set the corresponding port direction
registers to output mode.
Fig. 20 Structure of timer X mode register
Timer X mode register
(TXM : address 0027
16
)
Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
P5
2
data for real time port
P5
3
data for real time port
Timer X operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR
0
active edge switch bit
0 : Count at rising edge in event counter mode
Start from
“
H
”
output in pulse output mode
Measure
“
H
”
pulse width in pulse width
measurement mode
Falling edge active for CNTR
0
interrupt
1 : Count at falling edge in event counter mode
Start from
“
L
”
output in pulse output mode
Measure
“
L
”
pulse width in pulse width
measurement mode
Rising edge active for CNTR
0
interrupt
Timer X stop control bit
0 : Count start
1 : Count stop
b7
b0
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