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參數(shù)資料
| 型號(hào)： | 74VHC4046MTC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Phase Lock Loop |
| 中文描述： | PHASE LOCKED LOOP, 12 MHz, PDSO16 |
| 封裝： | 4.40 MM, MO-153, TSSOP-16 |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大?。?/td> | 283K |
| 代理商： | 74VHC4046MTC |
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Detailed Circuit Description
(Continued)
Thus in normal operation V
CC
and ground voltage levels are
fed to the loop filter. This differs from some phase detectors
which supply a current output to the loop filter and this
should be considered in the design. (The CD4046 also pro-
vides a voltage.)
Figure 5 shows the state tables for all three comparators.
PHASE COMPARATOR I
This comparator is a simple XOR gate similar to the
54/74HC86, and its operation is similar to an overdriven
balanced modulator. To maximize lock range the input fre-
quencies must have a 50% duty cycle. Typical input and
output waveforms are shown in Figure 4. The output of the
phase detector feeds the loop filter which averages the out-
put voltage. The frequency range upon which the PLL will
lock onto if initially out of lock is defined as the capture
range. The capture range for phase detector I is dependent
on the loop filter employed. The capture range can be as
large as the lock range which is equal to the VCO frequency
range.
To see how the detector operates refer to Figure 4. When
two square wave inputs are applied to this comparator, an
output waveform whose duty cycle is dependent on the
phase difference between the two signals results. As the
phase difference increases the output duty cycle increases
and the voltage after the loop filter increases. Thus in order
to achieve lock, when the PLL input frequency increases the
VCO input voltage must increase and the phase difference
between comparator in and signal in will increase. At an
input frequency equal f
min
, the VCO input is at 0V and this
requires the phase detector output to be ground hence the
two input signals must be in phase. When the input frequen-
cy is f
max
then the VCO input must be V
CC
and the phase
detector inputs must be 180
§
out of phase.
The XOR is more susceptible to locking onto harmonics of
the signal input than the digital phase detector II. This can
be seen by noticing that a signal 2 times the VCO frequency
results in the same output duty cycle as a signal equal the
VCO frequency. The difference is that the output frequency
of the 2f example is twice that of the other example. The
loop filter and the VCO range should be designed to prevent
locking on to harmonics.
PHASE COMPARATOR II
This detector is a digital memory network. It consists of four
flip-flops and some gating logic, a three state output and a
phase pulse output as shown in Figure 6. This comparator
acts only on the positive edges of the input signals and is
thus independent of signal duty cycle.
Phase comparator II operates in such a way as to force the
PLL into lock with 0 phase difference between the VCO
output and the signal input positive waveform edges.Figure
7 shows some typical loop waveforms. First assume that
the signal input phase is leading the comparator input. This
Phase Comparator State Diagrams
TL/F/11675–21
FIGURE 5. PLL State Tables
10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74VHC4046MTCX | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lock Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74VHC4046MTCX_NL | 功能描述:鎖相環(huán) - PLL FINISHED GOOD RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74VHC4046MX | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lock Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74VHC4046N | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lock Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74VHC4046NX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CMOS Phase Lock Loop |
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