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參數(shù)資料
| 型號： | 74LVTH16501MEA |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary |
| 中文描述： | LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.300 INCH, MO-118, SSOP-56 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 64K |
| 代理商： | 74LVTH16501MEA |
www.fairchildsemi.com
2
7
Connection Diagram
Pin Descriptions
Function Table
(Note 1)
H
=
HIGH Voltage Level
X
=
Immaterial
↑
=
LOW-to-HIGH Clock Transition
Note 1:
A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA. OEBA is active LOW
Note 2:
Output level before the indicated steady-state input conditions
were established, provided that CLKAB was HIGH before LEAB went LOW.
Note 3:
Output level before the indicated steady-state input conditions
were established.
L
=
LOW Voltage Level
Z
=
High Impedance
Functional Description
For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A
data is latched if CLKAB is held at a HIGH or LOW logic
level. If LEAB is LOW, the A bus data is stored in the latch/
flip-flop on the LOW-to-HIGH transition of CLKAB. Output-
enable OEAB is active-HIGH. When OEAB is HIGH, the
outputs are active. When OEAB is LOW, the outputs are in
the high-impedance state.
Data flow for B to A is similar to that of A-to-B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active-HIGH and OEBA is active-
LOW).
Logic Diagram
Pin Names
A
1
–
A
18
B
1
–
B
18
CLKAB, CLKBA Clock Pulse Inputs
LEAB, LEBA
Latch Enable Inputs
OEAB, OEBA
Output Enable Inputs
Description
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
Inputs
Output
B
n
Z
L
H
L
H
B
0
(Note 2)
B
0
(Note 3)
OEAB
L
H
H
H
H
H
H
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
↑
↑
H
L
A
n
X
L
H
L
H
X
X
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVTH16501MEA_Q | 功能描述:總線收發(fā)器 UB Transceiver 18Bit RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16501MEAX | 功能描述:總線收發(fā)器 UB Transceiver LV 18Bit 3State RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16501MTD | 功能描述:總線收發(fā)器 UB Transceiver 18Bit RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16501MTD_Q | 功能描述:總線收發(fā)器 UB Transceiver 18Bit RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16501MTDX | 功能描述:總線收發(fā)器 UB Transceiver LV 18Bit 3State RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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