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參數(shù)資料
| 型號： | 74LVTH16543 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Octal Bus Transceivers And Registers With 3-State Outputs 24-SOIC -40 to 85 |
| 中文描述： | 低電壓16位注冊收發(fā)器三態(tài)輸出 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 76K |
| 代理商： | 74LVTH16543 |
2001 Fairchild Semiconductor Corporation
DS012449
www.fairchildsemi.com
January 2000
Revised October 2001
7
74LVT16543
74LVTH16543
Low Voltage 16-Bit Registered Transceiver
with 3-STATE Outputs
General Description
The LVT16543 and LVTH16543 16-bit transceivers
contain two sets of D-type latches for temporary storage of
data flowing in either direction. Separate Latch Enable and
Output Enable inputs are provided for each register to per-
mit independent control of inputting and outputting in either
direction of data flow. Each byte has separate control
inputs, which can be shorted together for full 16-bit opera-
tion.
The LVTH16543 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These transceivers are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT16543 and
LVTH16543 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
I
Input and output interface capability to systems at
5V V
CC
I
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16543)
I
Also available without bushold feature (74LVT16543)
I
Live insertion/extraction permitted
I
Power Up/Down high impedance provides glitch-free
bus loading
I
Outputs source/sink
32 mA/
+
64 mA
I
Functionally compatible with the 74 series 16543
I
Latch-up conforms to JEDEC JED78
I
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
74LVT16543MEA
(Preliminary)
74LVT16543MTD
(Preliminary)
74LVTH16543MEA
74LVTH16543MTD
Package Number
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MS56A
MTD56
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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| 74LVTH16543MEA | Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs |
| 74LVTH16543MTD | Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs |
| 74LVTH16646 | Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs |
| 74LVTH16646MEA | Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs |
| 74LVTH16646MTD | Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVTH16543_ZAB3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74LVTH16543_ZAB3116B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74LVTH16543DGGRE4 | 功能描述:總線收發(fā)器 3.3V ABT 16-Bit Reg Trncvr W/3-St Otpt RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16543DGGRG4 | 功能描述:總線收發(fā)器 3.3V ABT 16B Reg Xcvr RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16543DLRG4 | 功能描述:總線收發(fā)器 3.3V ABT 16-Bit Reg Trncvr W/3-St Otpt RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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