參數(shù)資料
型號: 74LV574PWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Octal D-type flip-flop; positive edge-trigger 3-State
中文描述: LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
文件頁數(shù): 6/12頁
文件大?。?/td> 121K
代理商: 74LV574PWDH
Philips Semiconductors
Product specification
74LV574
Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10
6
AC CHARACTERISTICS
GND = 0V; t
r
= t
f
2.5ns; C
L
= 50pF; R
L
= 1K
SYMBOL
PARAMETER
WAVEFORM
CONDITION
LIMITS
–40 to +85
°
C
TYP
80
27
20
15
2
70
24
18
13
2
75
27
21
16
2
9
6
5
2
10
4
3
2
2
–10
–4
–3
–2
2
40
58
70
2
LIMITS
–40 to +125
°
C
MIN
41
30
24
26
19
15
5
5
5
12
16
20
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
2.0
2.7
3.0 to 3.6
MIN
34
25
20
22
16
13
5
5
5
15
19
24
MAX
34
25
20
17
34
25
20
17
27
21
17
15
MAX
43
31
25
21
43
31
25
21
34
26
21
18
Propagation delay
CP to Qn
t
PHL/
t
PLH
Figure 1, 4
ns
3-State output
3 State out ut
enable time
OE t Q
OE to Qn
t
PZH/
t
PZL
Figure 2, 4
ns
3-State output
3 State out ut
disable time
OE t Q
OE to Qn
t
PHZ/
t
PLZ
Figure 2, 4
ns
Clock pulse width
HIGH or LOW
t
W
Figure 1
ns
t
su
Set-up time
Dn to CP
Figure 3
ns
t
h
Hold time
Dn to CP
Figure 3
ns
Maximum clock
pulse frequency
f
max
Figure 1
MHz
NOTE:
1. Unless otherwise stated, all typical values are at T
amb
= 25
°
C.
2. Typical value measured at V
CC
= 3.3V.
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