參數(shù)資料
型號: 74LV574PWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Octal D-type flip-flop; positive edge-trigger 3-State
中文描述: LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
文件頁數(shù): 2/12頁
文件大?。?/td> 121K
代理商: 74LV574PWDH
Philips Semiconductors
Product specification
74LV574
Octal D-type flip-flop; positive edge-trigger (3-State)
2
1998 Jun 10
853-1990 19545
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce)
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot)
T
amb
= 25
°
C
Common 3-State output enable input
Output capability: bus driver
I
CC
category: MSI
0.8V at V
CC
= 3.3V,
2V at V
CC
= 3.3V,
DESCRIPTION
The 74LV574 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT574.
The 74LV574 is an octal D-type flip–flop featuring separate D-type
inputs for each flip-flop and non-inverting 3-state outputs for bus
oriented applications. A clock (CP) and an output enable (OE) input
are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that
meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition.
When OE is LOW, the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
=t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP to Q
n
C
L
= 15pF
V
CC
= 3.3V
13
ns
f
max
C
I
C
PD
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
x f
i
(C
L
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
Maximum clock frequency
C
L
= 15pF, V
CC
= 3.3V
77
MHz
Input capacitance
3.5
pF
Power dissipation capacitance per flip-flop
Notes 1 and 2
25
pF
V
CC2
f
o
) where:
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic DIL
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
74LV574 N
74LV574 N
SOT146-1
20-Pin Plastic SO
74LV574 D
74LV574 D
SOT163-1
20-Pin Plastic SSOP Type II
74LV574 DB
74LV574 DB
SOT339-1
20-Pin Plastic TSSOP Type I
74LV574 PW
74LV574PW DH
SOT360-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
Output enabled input (active LOW)
2, 3, 4, 5,
6, 7, 8, 9
D0–D7
Data inputs
19, 18, 17, 16,
15, 14, 13, 12
Q0–Q7
3-State flip-flop outputs
10
GND
Ground (0V)
11
CP
Clock input (LOW-to-HIGH,
edge-triggered)
20
VCC
Positive supply voltage
FUNCTION TABLE
OPERATING
MODES
INPUTS
INTERNAL
FLIP-FLOPS
OUTPUTS
OE
CP
Dn
Q0 to Q7
Load and read
register
L
L
l
h
L
H
L
H
Load register and
disable outputs
H
H
l
h
L
H
Z
Z
H
h
L
l
=
=
HIGH voltage level
HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
LOW voltage level
LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
High impedance OFF-state
LOW–to–HIGH clock transition
=
=
Z
=
=
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