參數(shù)資料
型號: 74HCT564
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85
中文描述: 八路D型觸發(fā)器;陽性沿觸發(fā),3態(tài);反相
文件頁數(shù): 7/7頁
文件大?。?/td> 58K
代理商: 74HCT564
December 1990
7
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
AC WAVEFORMS
Fig.6
Waveforms showing the clock (CP) to
output (Q
n
) propagation delays, the clock
pulse width, the output transition times and
the maximum clock pulse frequency.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.7
Waveforms showing the data set-up and
hold times for the data input (D
n
).
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.8
Waveforms showing the 3-state enable and
disable times.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
相關(guān)PDF資料
PDF描述
74HC564 Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
74HCT564D Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
74HCT564N 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85
74HCT573 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85
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