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參數(shù)資料
| 型號(hào)： | 74HCT564 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85 |
| 中文描述： | 八路D型觸發(fā)器;陽(yáng)性沿觸發(fā)，3態(tài);反相 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大小： | 58K |
| 代理商： | 74HCT564 |
December 1990
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
74HC/HCT564
FEATURES
3-state inverting outputs for bus oriented applications
8-bit positive-edge triggered register
Common 3-state output enable input
Independent register and 3-state buffer operation
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT564 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT564 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable (OE) input are common to all
flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are
available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The “564” is functionally identical to the “574” but has
inverting outputs. The “564” is functionally identical to the
“534”, but has a different pinning.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
; for HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
f
max
C
I
C
PD
propagation delay CP to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
C
L
= 15 pF; V
CC
= 5 V
15
127
3.5
27
16
62
3.5
27
ns
MHz
pF
pF
notes 1 and 2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74HC564 | Octal D-type flip-flop; positive-edge trigger; 3-state; inverting |
| 74HCT564D | Octal D-type flip-flop; positive-edge trigger; 3-state; inverting |
| 74HCT564N | 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85 |
| 74HCT573 | 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| 74HCT573 | 制造商:Misc 功能描述: |
| 74HCT573 HAR | 制造商:HAR 功能描述:74HCT573 NOTES |
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| 74HCT573BQ | 制造商:NXP Semiconductors 功能描述:Latch Transparent 3-ST 8-CH D-Type 20-Pin DHVQFN EP T/R Cut Tape 制造商:NXP Semiconductors 功能描述:IC OCTAL D-LATCH 3-ST DHVQFN20 制造商:NXP Semiconductors 功能描述:IC, OCTAL, D-LATCH, 3-ST, DHVQFN20, Latch Type:D Type Transparent, Output Curren |
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