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參數(shù)資料
| 型號(hào)： | 74F109 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual JK Positive Edge-Triggered Flip-Flop |
| 中文描述： | 雙JK上升沿觸發(fā)器 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 85K |
| 代理商： | 74F109 |
Philips Semiconductors
Product specification
74F109
Postive J-K positive edge-triggered flip-flops
October 23, 1990
5
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
M
V
M
CPn
V
M
V
M
V
M
V
M
V
M
V
M
t
su
(H)
t
h
(H)
Jn, Kn
Qn
V
M
t
w
(H)
1/f
max
t
su
(L)
t
h
(L)
V
M
V
M
t
PLH
Qn
t
w
(L)
t
PHL
t
PHL
t
PLH
SF00139
Waveform 1. Propagation Delay for Data to Output, Data Setup
Time and Hold Times, and Clock Width,and Maximum
Clock Frequency
V
M
V
M
RDn
V
M
Qn
V
M
V
M
V
M
t
PLH
Qn
t
w
(L)
t
PHL
t
PHL
t
PLH
SDn
V
M
V
M
t
w
(L)
SF00050
Waveform 2. Propagation Delay for Set and Reset to Output,
Set and Reset Pulse Width
SDn or RDn
V
M
V
M
t
rec
CPn
SF00051
Waveform 3. Recovery Timer for Set or Reset to Clock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F109PC | Dual JK Positive Edge-Triggered Flip-Flop |
| 74F109SC | Dual JK Positive Edge-Triggered Flip-Flop |
| 74F109SJ | Dual JK Positive Edge-Triggered Flip-Flop |
| 74F112 | Dual J-K negative edge-triggered flip-flop |
| 74F112 | Dual JK Negative Edge-Triggered Flip-Flop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F109_00 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual JK Positive Edge-Triggered Flip-Flop |
| 74F109_XGH3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F109D | 制造商:North American Philips Discrete Products Div 功能描述:Flip Flop, Dual, J/K Type, 16 Pin, Plastic, SOP 制造商:NXP Semiconductors 功能描述:Flip Flop, Dual, J/K Type, 16 Pin, Plastic, SOP |
| 74F109DC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 74F109LC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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