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參數(shù)資料
| 型號： | 74ALVCH16373T |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 16-Bit Transparent Latch with Bushold |
| 中文描述： | ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 95K |
| 代理商： | 74ALVCH16373T |
2002 Fairchild Semiconductor Corporation
DS500631
www.fairchildsemi.com
October 2001
Revised February 2002
7
74ALVCH16373
Low Voltage 16-Bit Transparent Latch with Bushold
General Description
The ALVCH16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the setup time is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
outputs are in a high impedance state.
The ALVCH16373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH16373 is designed for low voltage (1.65V to
3.6V) V
CC
applications with output compatibility up to 3.6V.
The 74ALVCH16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I
1.65V to 3.6V V
CC
supply operation
I
3.6V tolerant control inputs and outputs
I
Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
I
t
PD
(I
n
to O
n
)
3.6 ns max for 3.0V to 3.6V V
CC
4.5 ns max for 2.3V to 2.7V V
CC
6.8 ns max for 1.65V to 1.95V V
CC
I
Uses patented noise/EMI reduction circuitry
I
Latch-up conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
Package
Number
MTD48
Package Description
74ALVCH16373T
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ALVCH16373 | Low Voltage 16-Bit Transparent Latch with Bushold |
| 74ALVCH16373TX | LATCH|DUAL|8-BIT|AVC/ALVC-CMOS|TSSOP|48PIN|PLASTIC |
| 74ALVCH16374 | Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 85 |
| 74ALVCH16374T | Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 85 |
| 74ALVCH16374TX | FLIP-FLOP|16-BIT|D TYPE|AVC/ALVC-CMOS|TSSOP|48PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVCH16373T_Q | 功能描述:閉鎖 16-Bit Transparent L RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVCH16373TTR | 功能描述:閉鎖 16-Bit "D" Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVCH16373TX | 功能描述:閉鎖 Transparent Latch LV 16Bit RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVCH16373ZQLR | 功能描述:閉鎖 16B Transp D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVCH16373ZRDR | 功能描述:閉鎖 16B Trans D-Type Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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