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參數(shù)資料
| 型號： | 74ACT652SPC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Transceiver/Register |
| 中文描述： | ACT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-24 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 89K |
| 代理商： | 74ACT652SPC |
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7
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples in Figure 1 demonstrate the four fundamen-
tal bus-management functions that can be performed with
the Octal bus transceivers and receivers.
Data on the A or B data bus, or both can be stored in the
internal D-type flip-flop by LOW to HIGH transitions at the
appropriate Clock Inputs (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer mode, it is also possible to store data
without using the internal D-type flip-flops by simulta-
neously enabling OEAB and OEBA. In this configuration
each Output reinforces its Input. Thus when all other data
sources to the two sets of bus lines are in a HIGH imped-
ance state, each set of bus lines will remain at its last state.
FIGURE 1.
Note A: Real-Time
Transfer Bus B to Bus A
Note B: Real-Time
Transfer Bus A to Bus B
OEAB
L
OEBA
L
CPAB
X
CPBA
X
SAB
X
SBA
L
OEAB
H
OEBA
H
CPAB
X
CPBA
X
SAB
L
SBA
X
Note C: Storage
Note D: Transfer Storage
Data to A or B
OEAB
X
L
L
OEBA
H
X
H
CPAB
CPBA
X
SAB
X
X
X
SBA
X
X
X
OEAB
H
OEBA
L
CPAB
H or L
CPBA
H or L
SAB
H
SBA
H
X
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