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參數(shù)資料
| 型號(hào)： | 74ACT652SPC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Transceiver/Register |
| 中文描述： | ACT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-24 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 89K |
| 代理商： | 74ACT652SPC |
2000 Fairchild Semiconductor Corporation
DS500310
www.fairchildsemi.com
August 1999
Revised September 2000
7
74ACT652
Transceiver/Register
General Description
The ACT652 consists of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to the
HIGH logic level. Output Enable pins (OEAB, OEBA) are
provided to control the transceiver function.
Features
I
Independent registers for A and B buses
I
Multiplexed real-time and stored data
I
Outputs source/sink 24 mA
I
TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT
is a trademark of Fairchild Semiconductor Corporation.
Order Number
74ACT652SC
74ACT652MTC
74ACT652SPC
Package Number
M24B
MTC24
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
A
0
–
A
7
, B
0
–
B
7
CPAB, CPBA
A and B Inputs/3-STATE Outputs
Clock Inputs
SAB, SBA
Select Inputs
OEAB, OEBA
Output Enable Inputs
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