參數(shù)資料
型號： 74ACT2708PC
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 64 x 9 First-In, First-Out Memory
中文描述： 64 X 9 OTHER FIFO, 34.5 ns, PDIP28
封裝： 0.600 INCH, PLASTIC, MS-010, DIP-28
文件頁數(shù)： 7/13頁
文件大?。?/td> 95K
代理商： 74ACT2708PC
7
www.fairchildsemi.com
7
Mode 4: Shift-Out Sequence, FIFO Full to Empty
Sequence of Operation
1. FIFO is initially full and OR is HIGH, indicating valid
data is at the output. IR is LOW.
2. SO goes HIGH, resulting in OR going LOW one propa-
gation delay, t
OR
, after SO rises. OR LOW indicates
output stage is busy.
3. SO goes LOW, new data reaches output one propaga-
tion delay, t
D
, after SO falls; OR goes HIGH one propa-
gation delay, t
OR
, after SO falls and HF rises one
propagation delay, t
OF
, after SO falls. IR rises one fall-
through time, t
FT
, after SO falls.
4. Repeat process through the 64th SO pulse. FULL flag
goes LOW one propagation delay, t
OHF
, after the rising
edge of 33rd SO, indicating that the FIFO is less than
half full. On the falling edge of the 64th SO, HF goes
LOW one propagation delay, t
OE
, after SO, indicating
the FIFO is empty. The SO pulse may rise and fall
again with an attempt to unload an empty FIFO. This
results in no change in the data on the outputs as the
64th word stays latched.
Note:
SI and OE are LOW; MR is HIGH; D
0
–D
8
are immaterial.
FIGURE 4. Modes of Operation Mode 4
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