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參數(shù)資料
| 型號： | 74ACT2708PC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64 x 9 First-In, First-Out Memory |
| 中文描述： | 64 X 9 OTHER FIFO, 34.5 ns, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, MS-010, DIP-28 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 95K |
| 代理商： | 74ACT2708PC |
www.fairchildsemi.com
4
7
MODES OF OPERATION
Mode 1: Shift in Sequence for FIFO Empty to Full
Sequence of Operation
1. Input Ready is initially HIGH; HF and FULL flags are
LOW. The FIFO is empty and prepared for valid data.
OR is LOW indicating that the FIFO is not yet ready to
output data.
2. Shift-In is set HIGH, and data is loaded into the FIFO.
Data has to be settled t
s
before the falling edge of SI
and held t
h
after.
3. Input Ready (IR) goes LOW propagation delay t
IR
after
SI goes HIGH: input stage is busy.
4. Shift-In is set LOW; IR goes HIGH indicating the FIFO
is ready for additional data. Data just shifted-in arrives
at output propagation delay t
OD5
after SI falls. OR goes
HIGH propagation delay t
IOR
after SI goes LOW, indi-
cating the FIFO has valid data on its outputs. HF goes
HIGH propagation delay t
IE
after SI falls, indicating the
FIFO is no longer empty.
5. The process is repeated through the 64th data word.
On the rising edge of the 33rd SI, FULL flag goes HIGH
propagation delay t
IHF
after SI, indicating a half-full
FIFO. HF goes LOW propagation delay t
IF
after the ris-
ing edge of the 64th pulse indicating that the FIFO is
full. Any further shift-ins are disabled.
Note:
SO and OE are LOW; MR is HIGH.
FIGURE 1. Modes of Operation Mode 1
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