參數(shù)資料
型號： 74ACT16834
廠商： Texas Instruments, Inc.
英文描述： Dual 8-Bit To 9-Bit Parity Bus Transceivers.(雙8位-9位奇偶總線收發(fā)器)
中文描述： 雙8位至9位奇偶校驗(yàn)總線收發(fā)器。（雙8位-9位奇偶總線收發(fā)器）
文件頁數(shù)： 1/2頁
文件大小： 31K
代理商： 74ACT16834
54AC16834, 54ACT16834
74AC16834, 74ACT16834
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCAS405 – JUNE 1990
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of Texas Instruments Widebus
Family
Packaged in Shrink Small-Outline 300-mil
Packages (SSOP) and 380-mil Fine-Pitch
Ceramic Flat Packages Using 25-mil
Center-to-Center Pin Spacings
Inputs are TTL- or CMOS-Voltage
Compatible
3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture Optimizes PCB
Layout
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
μ
m Process
500-mA Typical Latch-Up Immunity at
125
°
C
description
The ’AC16834 and ’ACT16834 contain two
inverting 8-bit-to-9-bit parity bus transceivers. For
each transceiver, when data is transmitted from
the A bus to the B bus, an odd-parity bit is
generated and output on the parity I/O pin
(1PARITY or 2PARITY). When data is transmitted
from the B bus to the A bus, 1PARITY (or
2PARITY) is configured as an input and combined
with the B input data to generate an active-low
error flag if odd parity is not detected.
The error output (1ERR or 2ERR) is configured as
an open-collector output. The B-to-A parity error
flag is clocked into 1ERR (or 2ERR) on the
low-to-high transition of 1CLK (or 2CLK). 1ERR
(or 2ERR) is cleared (set high) by taking the clear
input 1CLR (or 2CLR) low.
The 74AC16834 and 74ACT16834 are packaged in TI’s shrink small-outline package (SSOP) with 25-mil
center-to-center pin spacings. This package provides twice the I/O pin count and functionality of a standard
small-outline package in the same printed-circuit-board area.
The ’AC16834 has CMOS-compatible input thresholds. The ’ACT16834 has TTL-compatible input thresholds.
The 54AC16834 and 54ACT16834 are characterized over the full military temperature range of –55
°
C to 125
°
C.
The 74AC16834 and 74ACT16834 are characterized for operation from –40
°
C to 85
°
C.
Copyright
1990, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
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1OEB
1CLK
1ERR
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2ERR
2CLK
2OEB
1OEA
1CLR
1PARITY
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2PARITY
2CLR
2OEA
74AC16834, 74ACT16834 . . . DL PACKAGE
54AC16834, 54ACT16834 . . . WD PACKAGE
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PDF描述
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74ACT16841DLR 功能描述:閉鎖 20B Bus-Interface D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
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