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參數(shù)資料
| 型號： | 74AC16843 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 18-Bit D-Type Latches With 3-State Outputs(18位D鎖存器(三態(tài)輸出)) |
| 中文描述： | 18位D類鎖存器與三態(tài)輸出（18位?鎖存器（三態(tài)輸出）） |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 20K |
| 代理商： | 74AC16843 |
54AC16843, 54ACT16843
74AC16843, 74ACT16843
18-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCAS407 – JUNE 1990
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1990, Texas Instruments Incorporated
1
PRODUCT PREVIEW information concerns products in
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
Members of Texas Instruments Widebus
Family
Packaged in Shrink Small-Outline 300-mil
Packages (SSOP) and 380-mil Fine-Pitch
Ceramic Flat Packages Using 25-mil
Center-to-Center Pin Spacings
Inputs are TTL- or CMOS-Voltage
Compatible
3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture Optimizes PCB
Layout
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
μ
m Process
500-mA Typical Latch-Up Immunity at
125
°
C
description
The ’AC16843 and ’ACT16843 are noninverting
18-bit D-type latches composed of two 9-bit
sections with separate control signals. For each
9-bit section, when the enable input 1C (or 2C) is
low, the latches are in the storage mode. In
contrast, when 1C (or 2C) is high, the latches are
transparent. In this mode, data present at the 1D
(or 2D) inputs is transmitted to the 1Q (or 2Q)
outputs if 1OE (or 2OE) is low. If 1OE (or 2OE) is
high, the corresponding outputs are in the
high-impedance state.
Preset (1PRE and 2PRE) and clear (1CLR and 2CLR) inputs are provided to set the corresponding Q outputs
asynchronously to a high or low logic level. Taking 1PRE (or 2PRE) low sets the corresponding outputs high.
If 1PRE (or 2PRE) is high, taking 1CLR (or 2CLR) low sets the corresponding outputs low.
The 74AC16843 and 74ACT16843 are packaged in TI’s shrink small-outline package (SSOP) with 25-mil
center-to-center pin spacings. This package provides twice the I/O pin count and functionality of a standard
small-outline package in the same printed-circuit-board area.
The ’AC16843 has CMOS-compatible input thresholds. The ’ACT16843 has TTL-compatible input thresholds.
The 54AC16843 and 54ACT16843 are characterized over the full military temperature range of –55
°
C to 125
°
C.
The 74AC16843 and 74ACT16843 are characterized for operation from –40
°
C to 85
°
C.
EPIC and Widebus are trademarks of Texas Instruments
Incorporated.
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1CLR
1OE
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q8
GND
2Q9
2OE
2CLR
1C
1PRE
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2PRE
16843, 74ACT16843 . . . DL PACKAGE
16843, 54ACT16843 . . . WD PACKAGE
(T0P VIEW)
2C
P
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| 74ACT16843 | 18-Bit D-Type Latches With 3-State Outputs(18位D鎖存器(三態(tài)輸出)) |
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