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參數(shù)資料
| 型號： | 74AC11833 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-Bit To 9-Bit Parity Bus Transceivers(8位-9位奇偶總線接收傳送器) |
| 中文描述： | 8位到第9位奇偶總線收發(fā)器（8位-9位奇偶總線接收傳送器） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 82K |
| 代理商： | 74AC11833 |
54AC11833, 74AC11833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2
Function Table
OEB
OEA
CLR
CLK
Ai
Σ
of H’s
Odd
Even
Bi
Σ
of H’s
INPUTS
A
B
PARITY
ERR
OUTPUT AND I/O
FUNCTION
L
H
X
X
NA
NA
A
L
H
NA
A data to B bus and
Generate Parity
B Data to A Bus and
Check Parity
Clear Error Flag Register
H
L
H
↑
NA
Odd
Even
X
B
NA
NA
H
L
H
X
X
L
X
X
X
NA
NA
H
H
H
L
H
H
No
↑
No
↑
↑
↑
X
X
Odd
Even
X
Z
Z
Z
NC
H
H
L
Isolation
L
L
X
X
Odd
Even
NA
NA
A
H
L
NA
A Data to B Bus and
Generate Inverted Parity
NA = Not applicable, NC = No change, X = Don’t care
Summation of high-level inputs includes PARITY along with Bi inputs.
In this mode, the ERR output, when clocked, shows inverted parity of the A bus.
logic diagram (positive logic)
8
8
EN
8
EN
8
8
PARITY
MUX
1
1
G1
9
2k
“P”
1D
C1
R
CLK
CLR
OPEN DRAIN
B1-B8
A1-A8
8
×
8
×
OEB
OEA
ERR
1
1
P
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