參數(shù)資料
型號(hào): 73M2910L
廠商: Electronic Theatre Controls, Inc.
英文描述: Microcontroller
中文描述: 微控制器
文件頁(yè)數(shù): 29/35頁(yè)
文件大?。?/td> 572K
代理商: 73M2910L
73M2910L
Microcontroller
29
DC CHARACTERISTICS
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Maximum Power Supply
power-down mode
IDD3
10
μA
Pin Capacitance
CIO
@1 MHz
10
pF
AC TIMING
The 73M2910L timing is very similar to the 8032 except in AD(7:0), the multiplexed address data port known
as port 0 in the 8032. Its timing has been altered somewhat to allow more address setup time for peripheral
program ROM and memory mapped peripherals. This is important for operation above 22 MHz. The 8032 has
a “dead” cycle of one oscillator period between the time PSEN goes high, indicating that the instruction ROM
will release the AD(7:0) bus, to the time the processor will assert address on the AD(7:0) bus. This dead time
of one whole oscillator cycle has been shortened to approximately 15 ns after the PSEN (or RD) signal is
sensed to be high.
The timing specification for TPXIZ and TRHDZ of a maximum of 20 ns can be violated at the expense of
increased operating current. The 73M2910L will begin asserting the AD(7:0) bus approximately 20 ns after
PSEN or RD go high. This should be ample time for the control signals in the peripheral device to turn off their
pad drivers. If the peripheral device does not release the bus promptly, there will be a short time where there
is contention on the AD(7:0) bus between the processor and peripheral. This should not prevent proper
operation, but it will increase operating current slightly.
EXTERNAL PROGRAM MEMORY READ TIMING
Oscillator Frequency
FOSC
0
44
MHz
Oscillator Period
TOSC
22.7
ns
ALE Pulse Width
TLHLL
2TOSC - 10
ns
Address Valid To ALE Low
TAVLL
TOSC
ns
Address Valid ALE Low
TLLAX
TOSC - 10
ns
ALE Low to PSEN Low
PSEN
Pulse Width Low
TLLPL
TOSC - 10
ns
TPLPH
3TOSC -
20
ns
PSEN
Low to Valid Inst In
TPLIV
3TOSC - 50
ns
Address to Valid Inst In
Input Instr Hold-
PSEN
High
PSEN Instr Float-
PSEN
High
TAVIV
6TOSC - 32
ns
TPXIX
0
ns
TPXIZ
20+
ns
PSEN Low to Address HighZ
TPLAZ
10
ns
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