參數(shù)資料
型號(hào)： 72841L10PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 4K X 9 BI-DIRECTIONAL FIFO, 6.5 ns, PQFP64
封裝： TQFP-64
文件頁(yè)數(shù)： 16/16頁(yè)
文件大?。?/td> 211K
代理商： 72841L10PF
9
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
NOTES:
1. Holding WENA2/
LDA (WENB2/LDB) HIGH during reset will make the pin act as a second write enable pin. Holding WENA2/LDA (WENB2/LDB) LOW
during reset will make the pin act as a load enable for the programmable flag offset registers.
2.
After reset, QA0 - QA8 (QB0 - QB8) will be LOW if
OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
3.
The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
Figure 4. Reset Timing
tRS
tRSR
RSA (RSB)
RENA1, RENA2
(
RENB1, RENB2)
tRSF
OEA (OEB) = 1
OEA (OEB) = 0
(2)
EFA, PAEA
(
EFB, PAEB)
FFA, PAFA
(
FFB, PAFB)
QA0 - QA8
(QB0 - QB8)
3034 drw 05
WENA1
(
WENB1)
tRSS
tRSF
tRSR
tRSS
tRSR
tRSS
WENA2/
LDA
(WENB2/
LDB)
(1)
NOTE:
1.
tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for
FFA (FFB) to change during the current clock cycle. If the time between
the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then
FFA (FFB) may not change state until the next WCLKA (WCLKB) edge.
Figure 5. Write Cycle Timing
tDH
tENH
tSKEW1(1)
tCLK
tCLKH
tCLKL
tDS
tENS
tWFF
WCLKA (WCLKB)
DA0 - DA8
(DB0 - DB8)
WENA1
(
WENB1)
WENA2 (WENB2)
(If Applicable)
FFA
(
FFB)
RCLKA (RCLKB)
RENA1, RENA2
(
RENB1, RENB2)
NO OPERATION
3034 drw 06
DATA IN VALID
tENS
tENH
相關(guān)PDF資料
PDF描述
72821L15TF8 1K X 9 BI-DIRECTIONAL FIFO, 10 ns, PQFP64
72R99-P 25 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK
72R99-M 25 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK
72R99-59 25 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK
72R99-49 25 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
72841L10PF8 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72841L10PFG 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72841L10PFG8 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 4KX9X2 64TQFP - Tape and Reel
72841L10TF 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72841L10TF8 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin STQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 4KX9X2 64TQFP - Tape and Reel
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