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參數(shù)資料
| 型號： | 72805LB15PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 256 X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 336K |
| 代理商： | 72805LB15PFI |
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
14
Figure 10. Single Register-Buffered Empty Flag Timing (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH during the current clock cycle. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW1, then
FF may not change state until the next WCLK edge.
2. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 9. Single Register-Buffered Full Flag Timing (IDT Standard Mode)
DATA READ
WCLK
D0 - D17
WEN
RCLK
FF
Q0 - Q17
tA
tWFF
DATA WRITE
REN
tWFF
tENH
tENS
tDS
tWFF
tDS
DATA
WRITE
NEXT DATA READ
tA
NO WRITE
DATA IN OUTPUT REGISTER
OE
LOW
tSKEW1
(1)
tSKEW1
(1)
tENH
tENS
3139 drw 09
WCLK
D0 - D17
WEN
RCLK
EF
Q0 - Q17
OE
tDS
tENS
tA
tSKEW1
DATA WRITE 1
DATA READ
tENH
tREF
tDS
tENS
DATA WRITE 2
tENH
tREF
REN
DATA IN OUTPUT REGISTER
tFRL
(1)
LOW
3139 drw 10
tREF
tSKEW1
tFRL
(1)
NOTES:
1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW1, or tCLK + tSKEW1. The Latency Timing
apply only at the Empty Boundary (
EF = LOW).
2. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 72805LB15PFI8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 256 x 18 x 2 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 256 X 18 X 2 128TQFP - Tape and Reel |
| 72805LB25BG | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 256 x 18 x 2 121-Pin BGA 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 256 X 18 X 2 121BGA - Rail/Tube |
| 72805LB25BG8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 256 x 18 x 2 121-Pin BGA T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 256 X 18 X 2 121BGA - Tape and Reel |
| 72805LB25PF | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72805LB25PF8 | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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