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參數資料
| 型號： | 722 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Dual Isolated DC/DC Converter(雙路隔離DC/DC變換器) |
| 中文描述： | 雙隔離式DC / DC轉換器（雙路隔離的DC / DC變換器） |
| 文件頁數： | 4/5頁 |
| 文件大?。?/td> | 84K |
| 代理商： | 722 |
4
722
TYPICAL PERFORMANCE CURVES
(CONT)
T
A
= +25
°
C, V
IN
= 15VDC, C = 0.47
μ
F. R
1
selected per Typical Performance Curve.
PARALLEL OUTPUT BALANCED
LOAD REGULATION
Output Load Current |I
L
| (mA)
O
L
|
16
15
14
13
0
20
40
60
80
100
V
L
L
I
L
I
L
V
V
V
PARALLEL OUTPUT UNBALANCED
LOAD REGULATION
Output Load Current |I
L
| (mA)
O
L
|
16
15
14
13
0
40
80
120
160
200
V
LI
L
I
F
V
V
O
V
O
I
F
= 100mA
I
F
= 6mA
I
F
= 32mA
INSTALLATION AND
OPERATING INSTRUCTIONS
Typical application connections for the 722 are shown in
Figures 1 and 3. Primary power (V
) is applied at the “P+”
and “V–” terminals. The common or ground for V
may be
connected to either “P+” or “V–”; the only requirement is
that “P+” and “V+” must be positive with respects to “V–”.
Power for the internal oscillator and switch drivers is de-
rived from the primary power by a voltage dropping resistor,
R
1
. The value of R
1
as a function of V
IN
is shown in the
Typical Performance Curves section. Alternately, voltage
for the “V+” terminal may be obtained from a separate
source. “V+” should be +5V to +7.5V positive with respect
to “V–.” If a separate source is used, the “V+” input must be
applied before the “P+” input to avoid possible damage to
the unit. “P+” and “V+” must remain positive with respect
to “V–” at all times (including transients). If necessary,
diode clamps should be put across these inputs.
The “E” pin enables the converter when connected to “V+”
and disables it when connected to “V–.”
An external capacitor, “C” (0.47
μ
F ceramic), is used to
reduce input ripple. It should be connected as close to the
“P+” and “V–” pins as practical. Input leads to these termi-
nals should also be kept as short as possible. Since the 722
is not internally shielded, external shielding may be appro-
priate in applications where RFI at the 900kHz nominal
oscillator frequency is a problem.
Each output is filtered with an internal 0.22
μ
F capacitor.
Output ripple voltage can be reduced below the specified
value by adding external capacitors up to 10
μ
F between
each output and its common.
OUTPUT-TO-OUTPUT INTERACTION
Output Load Current |I
L
| (mA)
O
N
|
16
15
14
13
0
40
80
120
160
200
V
L I
L
I
F
V
V
N
V
N
I
F
= 100mA
I
F
= 6mA
I
F
= 32mA
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 722 EN 0818/SB | 制造商:Ersa 功能描述: |
| 722 EN 1020/SB | 制造商:Ersa 功能描述: |
| 722.101 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TACHO 12-24VDC |
| 722.102 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TACHO 100-240VAC |
| 722.201 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SIGNO 722 TACHO 12-24VDC |
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