- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄357464 > 71V416YL12PHG2 (INTEGRATED DEVICE TECHNOLOGY INC) 256K X 16 STANDARD SRAM, 12 ns, PDSO44 PDF資料下載
參數(shù)資料
| 型號： | 71V416YL12PHG2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 16 STANDARD SRAM, 12 ns, PDSO44 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, TSOP2-44 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 206K |
| 代理商： | 71V416YL12PHG2 |
6.42
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
for Automotive Applications 4 Meg (256K x 16-Bit) Automotive Temperature Ranges
Timing Waveform of Read Cycle No. 2
(1)
ADDRESS
OE
CS
DATA
OUT
6817 drw 07
(3)
(3)
(3)
DATA
VALID
t
AA
t
RC
t
OE
t
OLZ
t
CHZ
t
OHZ
OUT
BHE
,
BLE
(3)
t
ACS
(3)
t
BLZ
t
CLZ
(2)
t
BE
t
OH
t
BHZ
(3)
(2)
V
DD
Supply
Current
I
CC
I
SB
t
PD
t
PU
NOTES:
1. A write occurs during the overlap of a LOW
CS
, LOW
BHE
or
BLE
, and a LOW
WE
.
2.
OE
is continuously HIGH. If during a
WE
controlled write cycle
OE
is LOW, t
WP
must be greater than or equal to t
WHZ
+ t
DW
to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the mnimumwrite pulse is as
short as the specified t
WP
.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the
CS
LOW or
BHE
and
BLE
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV fromsteady state.
Timing Waveform of Write Cycle No. 1 (
WE
Controlled Timing)
(1,2,4)
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of
CS
,
BHE
, or
BLE
transition LOW; otherwise t
AA
is the limting parameter.
3. Transition is measured ±200mV fromsteady state.
ADDRESS
CS
DATA
IN
6817 drw08
(5)
(5)
(5)
DATA
IN
VALID
t
WC
t
AS
t
WHZ
(2)
t
CW
t
CHZ
t
OW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
PREVIOUS DATA VALID
DATA VALID
BHE
,
BLE
t
BW
t
WP
(5)
t
BHZ
(3)
相關PDF資料 |
PDF描述 |
|---|---|
| 71V424VL15YGI | 512K X 8 STANDARD SRAM, 15 ns, PDSO36 |
| 72.000.0653.0 | 6-6 CONTACT(S), FEMALE-FEMALE, RECTANGULAR ADAPTER |
| 72.010.0653.0 | 6-6 CONTACT(S), MALE-MALE, RECTANGULAR ADAPTER |
| 72.005.0653.0 | 6-6 CONTACT(S), FEMALE-FEMALE, RECTANGULAR ADAPTER |
| 72.015.0653.0 | 6-6 CONTACT(S), MALE-MALE, RECTANGULAR ADAPTER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 71V416YS10PH8 | 制造商:Integrated Device Technology Inc 功能描述:IDT 71V416YS10PH8, 4MBit SRAM Chip Async Single 3.3V 256K x 16 10ns 44-Pin TSOP-II T/R |
| 71V416YS10PHG | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC SGL 3.3V 4MBIT 256KX16 10NS 44TSOP-II - Bulk |
| 71V416YS12BE18 | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC SGL 3.3V 4MBIT 256KX16 12NS 48CTBGA - Tape and Reel |
| 71V416YS12BEG1 | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC SGL 3.3V 4MBIT 256KX16 12NS 48CTBGA - Bulk |
| 71V416YS12PH3 | 制造商:Integrated Device Technology Inc 功能描述:FAST ASYNCH SRAM LOW POWER - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。