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| 型號： | 70T9169L12PF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 16K X 9 DUAL-PORT SRAM, 25 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 252K |
| 代理商： | 70T9169L12PF8 |
6.42
IDT70T9169/59L
High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
8
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for
that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL.
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)
70T9169/59L7
Com’l Only
70T9169/59L9
Com’l & Ind
70T9169/59L12
Com’l Only
Symbol
Parameter
Min.Max.Min.
Max.Min.
Max.
Unit
tCYC1
Clock Cycle Time (Flow-Through)(2)
22
____
25
____
30
____
ns
tCYC2
Clock Cycle Time (Pipelined)(2)
12
____
15
____
20
____
ns
tCH1
Clock High Time (Flow-Through)(2)
7.5
____
12
____
12
____
ns
tCL1
Clock Low Time (Flow-Through)(2)
7.5
____
12
____
12
____
ns
tCH2
Clock High Time (Pipelined)(2)
5
____
6
____
8
____
ns
tCL2
Clock Low Time (Pipelined)(2)
5
____
6
____
8
____
ns
tR
Clock Rise Time
____
3
____
3
____
3ns
tF
Clock Fall Time
____
3
____
3
____
3ns
tSA
Address Setup Time
4
____
4
____
4
____
ns
tHA
Address Hold Time
0
____
1
____
1
____
ns
tSC
Chip Enable Setup Time
4
____
4
____
4
____
ns
tHC
Chip Enable Hold Time
0
____
1
____
1
____
ns
tSB
Byte Enable Setup Time
4
____
4
____
4
____
ns
tHB
Byte Enable Hold Time
0
____
1
____
1
____
ns
tSW
R/
W Setup Time
4
____
4
____
4
____
ns
tHW
R/
W Hold Time
0
____
1
____
1
____
ns
tSD
Input Data Setup Time
4
____
4
____
4
____
ns
tHD
Input Data Hold Time
0
____
1
____
1
____
ns
tSAD
ADS Setup Time
4
____
4
____
4
____
ns
tHAD
ADS Hold Time
0
____
1
____
1
____
ns
tSCN
CNTEN Setup Time
4
____
4
____
4
____
ns
tHCN
CNTEN Hold Time
0
____
1
____
1
____
ns
tSRST
CNTRST Setup Time
4
____
4
____
4
____
ns
tHRST
CNTRST Hold Time
0
____
1
____
1
____
ns
tOE
Output Enable to Data Valid
____
7.5
____
9
____
12
ns
tOLZ
Output Enable to Output Low-Z(1)
2
____
2
____
2
____
ns
tOHZ
Output Enable to Output High-Z(1)
17
1
7
ns
tCD1
Clock to Data Valid (Flow-Through)(2)
____
18
____
20
____
25
ns
tCD2
Clock to Data Valid (Pipelined)(2)
____
7.5
____
9
____
12
ns
tDC
Data Output Hold After Clock High
2
____
2
____
2
____
ns
tCKHZ
Clock High to Output High-Z(1)
29
2
9
ns
tCKLZ
Clock High to Output Low-Z(1)
2
____
2
____
2
____
ns
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____
28
____
35
____
40
ns
tCCS
Clock-to-Clock Setup Time
____
10
____
15
____
15
ns
5654 tbl 11
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 70T9169PF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2.5V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
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