參數(shù)資料
型號(hào)： 7005
廠商： Aeroflex Inc.
英文描述： ACT7005/7006 Single Package Solution Dual Transceiver, Protocol, Subsystem
中文描述： ACT7005/7006單一封裝解決方案雙收發(fā)器，協(xié)議，子系統(tǒng)
文件頁(yè)數(shù)： 5/29頁(yè)
文件大小： 452K
代理商： 7005
Aeroflex Circuit Technology
SCD7005 REV B 8/2/01
Plainview NY (516) 694-6700
5
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
DD
Logic Supply
4.5
5.0
5.5
VDC
V
IH
Input "1"
2.4
V
V
IL
Input "0"
0.6
V
I
L
Input I
-450
-600
-900
μA
Note 1A
I
IH
Input I
-250
-400
-750
μA
Note 1B
I
L
Input I
-50
-200
-800
μA
Note 1C
I
IH
Input I
-50
-200
-800
μA
Note 1D
I
L
Input I
-25
-125
-400
μA
Note 2A
I
IH
Input I
-25
-125
-400
μA
Note 2B
V
OH
Output "1"
2.4
VDC
Note 3A
V
OL
Output "0"
0.4
VDC
Note 3B
V
DD
Static I
50
mA
Note 4A
V
DD
Dynamic I
170
mA
Note 4B
Notes:
1.
V
DD
= 5.5V
A. For RTAD0/1/2/3/4 and RTADPAR with VIL = 0.4V
B. For RTAD0/1/2/3/4 and RTADPAR with VIH = 2.4V
C. FOR BCSTEN WITH VIL = 0.4V, Test 1, 6MHz
D. FOR BCSTEN WITH VIH = 2.4V, Test 1, 6MHz
2.
All remaining inputs and I/O
VDD = 5.5V
A. VIL = 0.4V
B. VIH = 2.4V
3.
A. VDD = 4.5V and IOH = 3mA
B. VDD = 5.5V and IOL = 3mA
4.
VDD = 5.5V
A. Clock Input = 6MHz (45-55% Duty Cycle / TTL Levels), All remaining inputs = VDD,
All Outputs = Open Circuit
B. During a 32 word FIFO to RAM or RAM to FIFO block
move
.
Table 5 – Logic Electrical Characteristics
(Over Full Temperature Range)
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